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tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 1 post office box 1443 ? houston, texas 77251?1443 high-performance static cmos technology ? 150 mhz (6.67-ns cycle time) ? low-power (1.8-v core, 3.3-v i/o) design ? 3.3-v flash programming voltage high-performance cpu (c28x) ? 16 x 16 and 32 x 32 mac operations ? 16 x 16 dual mac ? harvard bus architecture ? atomic operations ? fast interrupt response and processing ? unified memory programming model ? 4m linear program address reach ? 4g linear data address reach ? code-efficient (in c/c++ and assembly) ? tms320f24x/lf240x processor source code compatible on-chip memory ? up to 128k x 16 flash (8 x 4k and 6 x 16k sectors) ? 2k x 16 otp rom ? l0 and l1: 2 blocks of 4k x 16 single-access ram (saram) ? h0: 1 block of 8k x 16 saram ? m0 and m1: 2 blocks of 1k x 16 saram boot rom (4k x 16) ? with software boot modes ? standard math tables external interface (f2812) ? up to 1.5m total memory ? programmable wait states ? programmable read/write strobe timing ? four individual chip selects clock and system control ? dynamic pll ratio changes supported ? on-chip oscillator ? watchdog timer module three external interrupts peripheral interrupt expansion (pie) block that supports 45 peripheral interrupts 128-bit security key/lock ? protects flash/otp and l0/l1 saram ? prevents firmware reverse engineering motor control peripherals ? two event managers (eva, evb) ? compatible to 240x devices three 32-bit cpu-timers serial port peripherals ? serial peripheral interface (spi) ? two serial communications interfaces (scis), standard uart ? enhanced controller area network (ecan) ? multichannel buffered serial port (mcbsp) with spi mode 12-bit adc, 16 channels ? 2 x 8 channel input multiplexer ? two sample-and-hold ? single conversion time: 200 ns ? pipeline conversion time: 60 ns up to 56 individually programmable, multiplexed general-purpose input / output (gpio) pins advanced emulation features ? analysis and breakpoint functions ? real-time debug via hardware development tools include ? ansi c/c++ compiler/assembler/linker ? supports tms320c24x ? /240x instructions ? code composer studio ? ide ? dsp bios ? jtag scan controllers ? (ti or third-party) ? evaluation modules ? broad third-party digital motor control support low-power modes and power savings ? idle, standby, halt modes supported ? disable individual peripheral clocks package options ? 179-pin microstar bga ? with external interface (ghh) (f2812) ? 176-pin low-profile quad flatpack (lqfp) with external interface (pgf) (f2812) ? 128-pin lqfp without external interface (pbk) (f2810) temperature options: ? a: ?40 c to 85 c ? s: ?40 c to 125 c pr o du c t preview copyright ? 2001, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. tms320c24x, code composer studio, and microstar bga are trademarks of texas instruments. all trademarks are the property of their respective owners. ? ieee standard 1149.1?1990, ieee standard test-access port product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 2 post office box 1443 ? houston, texas 77251 ? 1443 device summary 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block diagram 4 . . . . . . . . . . . . . . . . . . . . . . . . pin functions 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory map 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c28x cpu 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus (harvard bus architecture) 16 . . . . . . . . . peripheral bus 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . real-time jtag and analysis 17 . . . . . . . . . . . . . . . . . . external interface (xintf) (f2812 only) 17 . . . . . . . . . flash 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m0, m1 sarams 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l0, l1, h0 sarams 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . boot rom 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . security 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral interrupt expansion (pie) block 19 . . . . . . . external interrupts (xint1, 2, 13, xnmi) 19 . . . . . . . . . oscillator and pll 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral clocking 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral frames 0, 1, 2 (pfn) 20 . . . . . . . . . . . . . . . . . general-purpose input/output (gpio) multiplexer 20 . 32-bit cpu-timers (0, 1, 2) 20 . . . . . . . . . . . . . . . . . . . . . motor control peripherals 20 . . . . . . . . . . . . . . . . . . . . . . serial port peripherals 21 . . . . . . . . . . . . . . . . . . . . . . . . . register map 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device emulation registers 24 . . . . . . . . . . . . . . . . . . . . . . external interface, xintf (f2812 only) 27 . . . . . . . . . . . . interrupts 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vector table mapping 36 . . . . . . . . . . . . . . . . . . . . . . . . . . pie vector map 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pie registers 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pie/cpu interrupt response 41 . . . . . . . . . . . . . . . . . . . external interrupts 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . system control 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . osc and pll block 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . pll-based clock module 50 . . . . . . . . . . . . . . . . . . . . . . . . external reference oscillator clock option 50 . . . . . . . . watchdog block 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes block 54 . . . . . . . . . . . . . . . . . . . . . . . . peripherals 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit cpu-timers 0/1/2 56 . . . . . . . . . . . . . . . . . . . . . . . . event manager modules (eva, evb) 61 . . . . . . . . . . . . . . enhanced analog-to-digital converter (adc) module 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . enhanced controller area network (ecan) module 71 . multichannel buffered serial port (mcbsp) module 75 . . serial communications interface (sci) module 79 . . . . . serial peripheral interface (spi) module 82 . . . . . . . . . . . gpio mux 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 97 . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 98 . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 98 . . . . . . . . . . . . . electrical characteristics over recommended operating free-air temperature range 99 . . . . . . . . mechanical data 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table of contents pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 3 post office box 1443 ? houston, texas 77251 ? 1443 device summary note that throughout this data sheet, f2810 is used to denote tms320f2810; f2812 is used to denote tms320f2812; and f28x is used to denote f2810 and f2812. table 1. hardware features of the f2810 and f2812 devices feature f2810 f2812 instruction cycle (at 150 mhz) 6.67 ns 6.67 ns single-access ram (saram) (16-bit word) 18k 18k 3.3-v on-chip flash (16-bit word) 64k 128k code security for on-chip flash/saram yes yes boot rom yes yes otp rom yes yes external memory interface ? yes event managers a and b (eva and evb) eva, evb eva, evb general-purpose (gp) timers 4 4 compare (cmp)/pwm 16 16 capture (cap)/qep channels 6/2 6/2 watchdog timer yes yes 12-bit adc yes yes channels 16 16 32-bit cpu timers 3 3 spi yes yes scia, scib scia, scib scia, scib can yes yes mcbsp yes yes digital i/o pins (shared) 56 56 external interrupts 3 3 supply voltage 1.8-v core, 3.3-v i/o 1.8-v core, 3.3-v i/o packaging 128-pin pbk 179-pin ghh 176-pin pgf product status: product preview (pp) advance information (ai) production data (pd) pp pp pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 4 post office box 1443 ? houston, texas 77251 ? 1443 functional block diagram m0 saram 1k x 16 cpu-timer 0 cpu-timer 1 int[12:1] clkin real-time jtag cpu-timer 2 peripheral bus c28x cpu h0 saram 8k 16 l0 saram 4k x 16 int14 nmi int13 memory bus m1 saram 1k x 16 flash 128k x 16 (f2812) 64k x 16 (f2810) boot rom 4k 16 ecan scia/scib 12-bit adc external interrupt control (xint1/2/13, xnmi) eva/evb memory bus otp 2k x 16 mcbsp system control (oscillator and pll + peripheral clocking + low-power modes + watchdog) fifo fifo pie (96 interrupts) ? rs spi fifo tint0 tint1 tint2 control address(19) data(16) external interface (xintf) ? 16 channels ? 45 of the possible 96 interrupts are used on f2810/f2812. ? xintf is not available on the f2810. gpio pins xrs x1/xclkin x2 xppldis protected by the code security module. xint13 g p i o m u x l1 saram 4k x 16 xnmi pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 5 post office box 1443 ? houston, texas 77251 ? 1443 179-pin ghh (ball grid array) (top view) 14 12 13 10 11 8 9 p m l j h k n 56 34 g e f d c 12 a b 7 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 6 post office box 1443 ? houston, texas 77251 ? 1443 176-pin pgf (low-profile quad flatpack) (top view) 89 88 45 44 132 133 176 1 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 7 post office box 1443 ? houston, texas 77251 ? 1443 128-pin pbk (low-profile quad flatpack) (top view) 64 33 65 32 96 1 97 128 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 8 post office box 1443 ? houston, texas 77251 ? 1443 pin functions table 2 specifies the signals on the f2810 and f2812 devices. all digital inputs are ttl-compatible. all outputs are 3.3 v with cmos levels. inputs are not 5-v tolerant. a 20- a resistor is used for pullup/down. table 2. signal descriptions name pin no. i/o/z drive pu/pd ? description xintf signals (2812 only) xa[18:0] o/z 19-bit address bus xd[15:0] i/o/z 16-bit data bus xmp/mc i pu microprocessor/microcomputer mode select xhold i pu external dma hold request xholda o/z external dma hold acknowledge xzcs0 o/z zone 0 chip select strobe xzcs1 o/z zone 1 chip select strobe xzcs2 o/z zone 2 chip select strobe xzcs6and7 o/z zone 6 and 7 chip select strobe xwe o/z write enable xrd o/z read enable xrnw o/z read not write select xready i pu input ready signal jtag and miscellaneous signals x1/xclkin i ? oscillator input or clock generator input x2 i ? oscillator output xppldis i pu disable pll when high testsel i pu test mode select signal xrs i/o pu device reset (in) and watchdog reset (out) test1 i/o ? flash test signal 1 test2 i/o ? flash test signal 2 jtag trst i pd jtag test-logic reset tck i jtag test clock tms i jtag test mode select tdi i jtag test data input tdo o/z jtag test data output emu0 i/o/z pu emulation/test trigger channel 0 emu1 i/o/z pu emulation/test trigger channel 1 ? pu = pin has internal pullup; pd = pin has internal pulldown pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 9 post office box 1443 ? houston, texas 77251 ? 1443 pin functions (continued) table 2. signal descriptions (continued) name pin no. i/o/z drive pu/pd ? description adc analog input signals adcin0[7:0] i 8 channel analog inputs adcin1[7:0] i 8 channel analog inputs adcrefp o adc reference output adcrefm o adc reference output adcresext o adc external current bias resistor avssrefbg i analog gnd avddrefbg i analog power adclo i common low side analog input agnd (2 pins) i analog gnd avdd (2 pins) i analog 3.3-v supply power signals v ddo 3.3-v i/o power pins v ss i/o ground pins cv dd 1.8-v cpu/core power pins cv ss cpu/core ground pins ? pu = pin has internal pullup; pd = pin has internal pulldown pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 10 post office box 1443 ? houston, texas 77251 ? 1443 pin functions (continued) table 2. signal descriptions (continued) gpio peripheral signal pin no. i/o/z drive pu/pd ? description gpio or peripheral signals gpioa or eva signals gpioa0 pwm1 (o) i/o/z pu gpio or pwm output pin #1 gpioa1 pwm2 (o) i/o/z pu gpio or pwm output pin #2 gpioa2 pwm3 (o) i/o/z pu gpio or pwm output pin #3 gpioa3 pwm4 (o) i/o/z pu gpio or pwm output pin #4 gpioa4 pwm5 (o) i/o/z pu gpio or pwm output pin #5 gpioa5 pwm6 (o) i/o/z pu gpio or pwm output pin #6 gpioa6 t1pwm_t1cmp (i) i/o/z pu gpio or timer 1 output gpioa7 t2pwm_t2cmp (i) i/o/z pu gpio or timer 2 output gpioa8 cap1_qep1 (i) i/o/z pu gpio or capture input #1 gpioa9 cap2_qep2 (i) i/o/z pu gpio or capture input #2 gpioa10 cap3_qepi1 (i) i/o/z pu gpio or capture input #3 gpioa11 tdira (i) i/o/z pu gpio or timer direction gpioa12 tclkina (i) i/o/z pu gpio or timer clock input gpioa13 c1trip (i) i/o/z pu gpio or compare 1 output trip gpioa14 c2trip (i) i/o/z pu gpio or compare 2 output trip gpioa15 c3trip (i) i/o/z pu gpio or compare 3 output trip gpiob or evb signals gpiob0 pwm7 (o) i/o/z pu gpio or pwm output pin #7 gpiob1 pwm8 (o) i/o/z pu gpio or pwm output pin #8 gpiob2 pwm9 (o) i/o/z pu gpio or pwm output pin #9 gpiob3 pwm10 (o) i/o/z pu gpio or pwm output pin #10 gpiob4 pwm11 (o) i/o/z pu gpio or pwm output pin #11 gpiob5 pwm12 (o) i/o/z pu gpio or pwm output pin #12 gpiob6 t3pwm_t3cmp (i) i/o/z pu gpio or timer 3 output gpiob7 t4pwm_t4cmp (i) i/o/z pu gpio or timer 4 output gpiob8 cap4_qep3 (i) i/o/z pu gpio or capture input #4 gpiob9 cap5_qep4 (i) i/o/z pu gpio or capture input #5 gpiob10 cap6_qepi2 (i) i/o/z pu gpio or capture input #6 gpiob11 tdirb (i) i/o/z pu gpio or timer direction gpiob12 tclkinb (i) i/o/z pu gpio or timer clock input gpiob13 c4trip (i) i/o/z pu gpio or compare 4 output trip gpiob14 c5trip (i) i/o/z pu gpio or compare 5 output trip gpiob15 c6trip (i) i/o/z pu gpio or compare 6 output trip gpiod or eva signals gpiod0 t1ctrip_pdpinta (i) i/o/z pu timer 1 compare output trip gpiod1 t2ctrip /evasoc (i) i/o/z pu timer 2 compare output trip or external adc start-of-conversion ev-a ? pu = pin has internal pullup; pd = pin has internal pulldown pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 11 post office box 1443 ? houston, texas 77251 ? 1443 pin functions (continued) table 2. signal descriptions (continued) gpio peripheral signal pin no. i/o/z drive pu/pd ? description gpiod or evb signals gpiod5 t3ctrip_pdpintb (i) i/o/z pu timer 3 compare output trip gpiod6 t4ctrip /evbsoc (i) i/o/z pu timer 4 compare output trip or external adc start-of-conversion ev-b gpioe or interrupt signals gpioe0 xint1_xbio (i) i/o/z pu gpio or xint1 or xbio core input gpioe1 xint2_adcsoc (i) i/o/z pu gpio or xint2 or adc start of conversion gpioe2 xnmi_xint13 (i) i/o/z pu gpio or xnmi or xint13 gpiof or spi signals gpiof0 spisimo (o) i/o/z pu gpio or spi slave in, master out gpiof1 spisomi (i) i/o/z pu gpio or spi slave out, master in gpiof2 spiclk (i/o) i/o/z pu gpio or spi clock gpiof3 spiste (i/o) i/o/z pu gpio or spi slave transmit enable gpiof or sci-a signals gpiof4 scitxda (o) i/o/z pu gpio or sci asynchronous serial port tx data gpiof5 scirxda (i) i/o/z pu gpio or sci asynchronous serial port rx data gpiof or can signals gpiof6 cantx (o) i/o/z pu gpio or ecan transmit data gpiof7 canrx (i) i/o/z pu gpio or ecan receive data gpiof or mcbsp signals gpiof8 mclkx (i/o) i/o/z pu gpio or transmit clock gpiof9 mclkr (i/o) i/o/z pu gpio or receive clock gpiof10 mfsx (i/o) i/o/z pu gpio or transmit frame synch gpiof11 mfsr (i/o) i/o/z pu gpio or receive frame synch gpiof12 mdx (o) i/o/z pu gpio or transmitted serial data gpiof13 mdr (i) i/o/z pu gpio or received serial data gpiog or xf cpu output signal gpiof14 xf(0) i/o/z pu gpio or input clock gpiog or sci-b signals gpiog4 scitxdb (o) i/o/z pu gpio or sci asynchronous serial port transmit data gpiog5 scirxdb (i) i/o/z pu gpio or sci asynchronous serial port receive data ? pu = pin has internal pullup; pd = pin has internal pulldown pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 12 post office box 1443 ? houston, texas 77251 ? 1443 memory map block start address low 64k (24x/240x equivalent data space) 0x0000 ? 0000 m0 vector ? ram (32 32) (enabled if vmap = 0) data space prog space m0 saram (1k 16) m1 saram (1k 16) peripheral frame 0 (2k 16) 0x0000 ? 0040 0x0000 ? 0400 0x0000 ? 0800 pie vector - ram (256 16) (enabled if vmap = 0, enpie = 1) reserved reserved reserved l0 saram (4k 16, secure block) peripheral frame 2 (4k 16, protected) reserved peripheral frame 1 (4k 16, protected) l1 saram (4k 16, secure block) reserved otp (2k 16, secure block) flash (128k 16, secure block) 128-bit password h0 saram (8k 16) reserved boot rom (4k 16) (enabled if mp/mc = 0) brom vector - rom (32 32) (enabled if vmap = 1, mp/mc = 0, enpie = 0) 0x0000 ? 0d00 0x0000 ? 1000 0x0000 ? 2000 0x0000 ? 6000 0x0000 ? 7000 0x0000 ? 8000 0x0000 ? 9000 0x0000 ? a000 0x003d ? 7800 0x003d ? 8000 0x003f ? 0000 0x003f ? 7ff8 0x003f ? 8000 0x003f ? a000 0x003f ? f000 0x003f ? ffc0 high 64k (24x/240x equivalent program space) data space prog space reserved xintf zone 0 (8k 16, xzcs0 ) xintf zone 1 (8k 16, xzcs1 ) (protected) reserved xintf zone 2 (0.5m 16, xzcs2 ) xintf zone 6 (1m 16, xzcs6and7 ) reserved xintf zone 7 (16k 16, xzcs6and7 ) (enabled if mp/mc = 1) xintf vector - ram (32 32) (enabled if vmap = 1, mp/mc = 1, enpie = 0) on-chip memory external memory xintf only one of these vector maps ? m0 vector, pie vector, brom vector, xintf vector ? should be enabled at a time. legend: 0x0008 ? 0000 0x0000 ? 4000 0x0010 ? 0000 0x0020 ? 0000 0x003f ? c000 notes: a. memory blocks are not to scale. b. reserved locations are reserved for future expansion. application should not access these areas. c. boot rom and zone 7 memory maps are active either in on-chip or xintf zone depending on mp/mc , not in both. d. peripheral frame 0, peripheral frame 1, and peripheral frame 2 memory maps are restricted to data memory only. user program cannot access these memory maps in program space. e. ? protected ? means the order of write followed by read operations is preserved rather than the pipeline order. f. certain memory ranges are eallow protected for spurious writes after configuration. g. zone 6 and zone 7 share the same chip select; hence, these memory blocks have mirrored locations. figure 1. f2812 memory map pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 13 post office box 1443 ? houston, texas 77251 ? 1443 memory map (continued) block start address low 64k (24x/240x equivalent data space) 0x0000 ? 0000 m0 vector ? ram (32 32) (enabled if vmap = 0) data space prog space m0 saram (1k 16) m1 saram (1k 16) peripheral frame 0 (2k 16) 0x0000 ? 0040 0x0000 ? 0400 0x0000 ? 0800 pie vector - ram (256 16) (enabled if vmap = 0, enpie = 1) reserved reserved reserved l0 saram (4k 16, secure block) peripheral frame 2 (4k 16, protected) reserved peripheral frame 1 (4k 16, protected) l1 saram (4k 16, secure block) reserved reserved flash (64k 16, secure block) 128-bit password h0 saram (8k 16) reserved boot rom (4k 16) (enabled if mp/mc = 0) brom vector - rom (32 32) (enabled if vmap = 1, mp/mc = 0, enpie = 0) 0x0000 ? 0d00 0x0000 ? 1000 0x0000 ? 2000 0x0000 ? 6000 0x0000 ? 7000 0x0000 ? 8000 0x0000 ? 9000 0x0000 ? a000 0x003d ? 8000 0x003e ? 0000 0x003f ? 0000 0x003f ? 7ff8 0x003f ? 8000 0x003f ? a000 0x003f ? f000 0x003f ? ffc0 high 64k (24x/240x equivalent program space) on-chip memory only one of these vector maps ? m0 vector, pie vector, brom vector ? should be enabled at a time. legend: otp (2k 16, secure block) 0x003d ? 7800 notes: a. memory blocks are not to scale. flash location subject to change. b. reserved locations are reserved for future expansion. application should not access these areas. c. boot rom and zone 7 memory maps are active either in on-chip or xintf zone depending on mp/mc , not in both. d. peripheral frame 0, peripheral frame 1, and peripheral frame 2 memory maps are restricted to data memory only. user program cannot access these memory maps in program space. e. ? protected ? means the order of write followed by read operations is preserved rather than the pipeline order. f. certain memory ranges are eallow protected for spurious writes after configuration. g. zone 6 and zone 7 share the same chip select; hence, these memory blocks have mirrored locations. figure 2. f2810 memory map pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 14 post office box 1443 ? houston, texas 77251 ? 1443 memory map (continued) the ? low 64k ? of the memory address range maps into the data space of the 240x. the ? high 64k ? of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only execute from the ? high 64k ? memory area. hence, the top 32k of flash and h0 saram block can be used to run 24x/240x-compatible code (if mp/mc mode is low) or, on f2812, code can be executed from xintf zone 7 (if mp/mc mode is high). the xintf consists of five independent zones. three zones have their own chip selects and two zones share a single chip select. each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. this makes interfacing to external peripherals easy and glueless. note: the chip selects of xintf zone 6 and zone 7 are merged together into a single chip select (zcs6and7 ). refer to the ? external interface ? xintf (f2812 only) ? section of this data sheet for details. peripheral frame 1, peripheral frame 2, and xintf zone 1 are grouped together so as to enable these blocks to be ? write/read peripheral block protected ? . the ? protected ? mode ensures that all accesses to these blocks happen as written. because of the c28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the cpu. this can cause problems in certain peripheral applications where the user expected the write to occur first (as written). the c28x cpu supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). this mode is programmable and by default, it will protect the selected zones. on the f2812, at reset, xintf zone 7 is enabled if the xmp/mc signal is pulled high. this signal selects microprocessor or microcomputer mode of operation. in microprocessor mode, zone 7 is mapped to high memory such that the vector table is fetched externally. the boot rom is disabled in this mode. in microcomputer mode, zone 7 is disabled such that the vectors are fetched from boot rom. this allows the user to either boot from on-chip memory or from off-chip memory. the state of the xmp/mc signal on reset is stored in an mp/mc mode bit in the xintcnf2 register. the user can change this mode in software and hence control the mapping of boot rom and xintf zone 7. no other memory blocks are affected by xmp/mc . i/o space is not supported on the f2812 xintf. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 15 post office box 1443 ? houston, texas 77251 ? 1443 memory map (continued) the wait states for the various spaces in the memory map area are listed in table 3. table 3. wait states area wait-states comments m0 & m1 sarams 0-wait peripheral frame 0 0-wait includes the flash registers. peripheral frame 1 0-wait (writes) 2-wait (reads) cycles can be extended by peripheral generated ready. peripheral frame 2 0-wait (writes) 2-wait (reads) fixed. cycles cannot be extended by the peripheral. l0 & l1 sarams 0-wait otp programmable, 0-wait minimum programmed via the flash registers. flash programmable, 0-wait minmum programmed via the flash registers. h0 saram 0-wait boot-rom 1-wait xintf programmable, 1-wait minimum programmed via the xintf registers. cycles can be extended by external memory or peripheral. 0-wait operation is not possible. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 16 post office box 1443 ? houston, texas 77251 ? 1443 description the tms320f2810 and tms320f2812 devices, members of the tms320c28x ? dsp generation, are highly integrated, high-performance solutions for demanding control applications. the functional blocks and the memory maps are described in subsequent paragraphs. c28x cpu the c28x ? dsp generation is the newest member of the tms320c2000 ? dsp platform. the c28x is source code compatible to the 24x/240x dsp devices, hence existing 240x users can leverage their significant software investment. additionally, the c28x is a very efficient c/c++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using c/c++. the c28x is as efficient in dsp math tasks as it is in system control tasks that typically are handled by microcontroller devices. this efficiency removes the need for a second processor in many systems. the 32 x 32-bit mac capabilities of the c28x and its 64-bit processing capabilities, enable the c28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. the c28x has an 8-level-deep protected pipeline with pipelined memory accesses. this pipelining enables the c28x to execute at high speeds without resorting to expensive high-speed memories. special branch-look-ahead hardware minimizes the latency for conditional discontinuities. special store conditional operations further improve performance. memory bus (harvard bus architecture) as with many dsp type devices, multiple busses are used to move data between the memories and peripherals and the cpu. the c28x memory bus architecture contains a program read bus, data read bus and data write bus. the program read bus consists of 22 address lines and 32 data lines. the data read and write busses consist of 32 address lines and 32 data lines each. the 32-bit-wide data busses enable single cycle 32-bit operations. the multiple bus architecture, commonly termed ? harvard bus ? , enables the c28x to fetch an instruction, read a data value and write a data value in a single cycle. all peripherals and memories attached to the memory bus will prioritize memory accesses. generally, the priority of memory bus accesses can be summarized as follows: highest: data writes ? program writes ? data reads program reads ? lowest: fetches ? peripheral bus to enable migration of peripherals between various texas instruments (ti) dsp family of devices, the f2810 and f2812 adopt a peripheral bus standard for peripheral interconnect. the peripheral bus bridge multiplexes the various busses that make up the processor ? memory bus ? into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. there are two versions of the peripheral bus supported on the f2810 and f2812. one version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with c240x compatible peripherals. the other version supports both 16- and 32-bit accesses (called peripheral frame 1) and is used to connect peripherals requiring higher throughput. pr o du c t preview tms320c28x, c28x, and tms320c2000 are trademarks of texas instruments. ? simultaneous data and program writes cannot occur on the memory bus. ? simultaneous program reads and fetches cannot occur on the memory bus.
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 17 post office box 1443 ? houston, texas 77251 ? 1443 real-time jtag and analysis the c28x implements the standard ieee 1149.1 jtag interface. additionally, the c28x supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. the user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. the c28x implements the real-time mode in hardware within the cpu. this is a unique feature to the c28x, no software monitor is required. additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs. external interface (xintf) (f2812 only) this asynchronous interface consists of 19 address lines, 16 data lines, and four chip-select lines. the chip-select lines are mapped to five external zones, zone 0, 1, 2, 6, and 7. zones 6 and 7 share a single chip-select. each of the five zones can be programmed with different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. the programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals. flash the f2812 contains 128k x16 of embedded flash memory and 2k x16 of otp memory. the flash memory is segregated into eight 4k x16 sized sectors, and six 16k x16 sized sectors. the user can individually erase, program and validate a sector while leaving other sectors untouched. special memory pipelining is provided to enable the flash module to achieve higher performance. the flash/otp is mapped to both program and data space hence can be used to execute code or store data information. the f2810 has 64k x 16 of embedded flash and 2k x 16 of otp memory. m0, m1 sarams all c28x devices will contain these two blocks of single access memory, each 1kx16 in size. the stack pointer points to the beginning of block m1 on reset. the m0 block overlaps the 240x device b0, b1, b2 ram blocks and hence the mapping of data variables on the 240x devices can remain at the same physical address on c28x devices. the m0 and m1 blocks, like all other memory blocks on c28x devices, are mapped to both program and data space. hence, the user can use m0 and m1 to execute code or for data variables. the partitioning is performed within the linker. the c28x device presents a unified memory map to the programmer. this makes for easier programming in high-level languages. l0, l1, h0 sarams the f2810 and the f2812 will contain an additional 16k x 16 of single-access ram, divided into 3 blocks (4k + 4k + 8k). each block can be independently accessed hence minimizing pipeline stalls. each block is mapped to both program and data space. boot rom the boot rom is factory programmed with boot loading software. boot-mode signals are provided to tell the boot loader software, programmed into the boot rom, what boot mode to use on power up. the user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal flash. the boot rom will also contain standard tables, such as sin/cos waveforms, for use in math related algorithms. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 18 post office box 1443 ? houston, texas 77251 ? 1443 security the f2810 and f2812 support high levels of security to protect the user firmware from being reversed engineered. the security features a 128-bit password, which the user programs into the flash. one code security module (csm) is used to protect the flash/otp and the l0/l1 saram blocks. the security feature prevents unauthorized users from examining the memory contents via the jtag port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. to enable access to the secure blocks, the user must write the correct 128-bit ? key ? value, which matches the value stored in the password locations within the flash. code security module disclaimer the code security module ( ? csm ? ) included on this device was designed to password protect the data stored in the associated memory (either rom or flash) and is warranted by texas instruments (ti), in accordance with its standard terms and conditions, to conform to ti ? s published specifications for the warranty period applicable for this device. ti does not, however, warrant or represent that the csm cannot be compromised or breached or that the data stored in the associated memory cannot be accessed through other means. moreover, except as set forth above, ti makes no warranties or representations concerning the csm or operation of this device, including any implied warranties of merchantability or fitness for a particular purpose. in no event shall ti be liable for any consequential, special, indirect, incidental, or punitive damages, however caused, arising in any way out of your use of the csm or this device, whether or not ti has been advised of the possibility of such damages. excluded damages include, but are not limited to loss of data, loss of goodwill, loss of use or interruption of business or other economic loss. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 19 post office box 1443 ? houston, texas 77251 ? 1443 peripheral interrupt expansion (pie) block the pie block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. the pie block can support up to 96 peripheral interrupts. on the f2810/f2812, 45 of the possible 96 interrupts are used by peripherals. the 96 interrupts are grouped into blocks of 8 and each group is fed into one of 12 cpu interrupt lines (int1 to int12 ). each of the 96 interrupts is, supported by its own vector stored in a dedicated ram block that can be overwritten by the user. the vector is, automatically fetched by the cpu on servicing the interrupt. it takes 9 cpu clock cycles to fetch the vector and save critical cpu registers. hence the cpu can quickly respond to interrupt events. prioritization of interrupts is controlled in hardware and software. each individual interrupt can be enabled/disabled within the pie block. external interrupts (xint1, 2, 13, xnmi) the f2810 and f2812 support three masked external interrupts (xint1, 2, 13). xint13 is combined with one non-masked external interrupt (xnmi). the combined signal name is xnmi_xint13. each of the interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled (including the xnmi). the masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. this counter can be used to accurately time stamp the interrupt. oscillator and pll the f2810 and f2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. a pll is provided supporting up to 10-input clock-scaling ratios. the pll ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. the pll block can be set in bypass mode. watchdog the f2810 and f2812 support a watchdog timer. the user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. the watchdog can be disabled if necessary. peripheral clocking the clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. additionally, the system clock to the serial ports and the event managers, cap and qep blocks can be scaled relative to the cpu clock. this enables the timing of peripherals to be decoupled from increasing cpu clock speeds. low-power modes the f2810 and f2812 devices are full static cmos devices. three low-power modes are provided: idle: place cpu into low-power mode. peripheral clocks may be turned off selectively and only those peripherals that need to function during idle are left operating. an enabled interrupt from an active peripheral will wake the processor from idle mode. standby: turn off clock to cpu and peripherals. this mode leaves the oscillator and pll functional. an external interrupt event will wake the processor and the peripherals. execution begins on the next valid cycle after detection of the interrupt event. halt: turn off oscillator. this mode basically shuts down the device and places it in the lowest possible power consumption mode. only a reset or xnmi will wake the device from this mode. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 20 post office box 1443 ? houston, texas 77251 ? 1443 peripheral frames 0, 1, 2 (pfn) the f2810 and f2812 segregate peripherals into three sections. the mapping of peripherals is as follows: pf0: xintf: external interface configuration registers pie: pie interrupt enable and control registers plus pie vector table flash: flash control, programming, erase, verify registers timers: cpu-timers 0, 1, 2 registers csm: code security module key registers pf1: ecan: ecan mailbox and control registers pf2: sys: system control registers gpio: gpio mux configuration and control registers ev: event manager (eva/evb) control registers mcbsp: mcbsp control and tx/rx registers sci: serial communications interface (sci) control and rx/tx registers spi: serial peripheral interface (spi) control and rx/tx registers adc: 12-bit adc registers general-purpose input/output (gpio) multiplexer most of the peripheral signals are multiplexed with general-purpose i/o (gpio) signals. this enables the user to use a pin as gpio if the peripheral signal or function is not used. on reset, all gpio pins are configured as inputs. the user can then individually program each pin for gpio mode or peripheral signal mode. for specific inputs, the user can also select the number of input qualification cycles. this is to filter unwanted noise glitches. 32-bit cpu-timers (0, 1, 2) cpu-timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. the timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. the counter is decremented at the cpu clock speed divided by the prescale value setting. when the counter reaches zero, it is automatically reloaded with a 32-bit period value. cpu-timers 1 and 2 are reserved for real-time os (rtos) applications. cpu-timer 2 is connected to int14 of the cpu. cpu-timer 1 can be connected to int13 of the cpu. cpu-timer 0 is for general use and is connected to the pie block. motor control peripherals the f2810 and f2812 support the following peripherals which, are used for controlling motors: ev: the event manager module includes general-purpose timers, full-compare/pwm units, capture inputs (cap) and quadrature-encoder pulse (qep) circuits. two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. the event managers on the f2810 and f2812 are compatible to the event managers on the 240x devices (with some minor enhancements). adc: the adc block is a 12-bit converter, single ended, 16-channels. it will contain two sample-and-hold units for simultaneous sampling. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 21 post office box 1443 ? houston, texas 77251 ? 1443 serial port peripherals the f2810 and f2812 support the following serial communication peripherals: ecan: this is the enhanced version of the can peripheral. it supports 32 mailboxes, time stamping of messages, and is can 2.0b-compliant. mcbsp: this is the multichannel buffered serial port that is used to connect to e1/t1 lines, phone-quality codecs for modem applications or high-quality stereo-quality audio dac devices. the mcbsp receive and transmit registers are supported by a 16-level fifo. this significantly reduces the overhead for servicing this peripheral. spi: the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multi-device communications are supported by the master/slave operation of the spi. on the f2810 and the f2812, the port supports a 16-level, receive and transmit fifo for reducing servicing overhead. sci: the serial communications interface is a two-wire asynchronous serial port, commonly known as uart. on the f2810 and the f2812, the port supports a 16-level, receive and transmit fifo for reducing servicing overhead. register map the f2810 device contains three peripheral register spaces. the spaces are categorized as follows: peripheral frame 0: these are peripherals that are mapped directly to the cpu memory bus. see table 4. peripheral frame 1: these are peripherals that are mapped to the 32-bit peripheral bus. see table 5. peripheral frame 2: these are peripherals that are mapped to the 16-bit peripheral bus. see table 6. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 22 post office box 1443 ? houston, texas 77251 ? 1443 register map (continued) table 4. peripheral frame 0 registers name address range size (x16) access type ? cpu emulation register space 0x0000 0800 0x0000 087f 128 eallow protected device emulation registers 0x0000 0880 0x0000 09ff 384 eallow protected reserved 0x0000 0a00 0x0000 0b00 128 flash registers ? 0x0000 0a80 0x0000 0adf 96 eallow protected csm protected code security module registers 0x0000 0ae0 0x0000 0aef 16 eallow protected reserved 0x0000 0af0 0x0000 0b1f 48 xintf registers 0x0000 0b20 0x0000 0b3f 32 not eallow protected reserved 0x0000 0b40 0x0000 0bff 192 cpu-timer0/1/2 registers 0x0000 0c00 0x0000 0c3f 64 not eallow protected reserved 0x0000 0c40 0x0000 0cdf 160 pie registers 0x0000 0ce0 0x0000 0cff 32 not eallow protected pie vector table 0x0000 0d00 0x0000 0dff 256 eallow protected reserved 0x0000 0e00 0x0000 0fff 512 ? if registers are eallow protected, then writes cannot be performed until the user executes the eallow instruction. the edis ins truction disables writes. this prevents stray code or pointers from corrupting register contents. ? the flash registers are also protected by the code security module (csm). table 5. peripheral frame 1 registers name address range size (x16) access type ecan registers 0x0000 6000 0x0000 61ff 512 user accessible reserved 0x0000 6200 0x0000 6fff 3584 peripheral frame 1 allows 16-bit and 32-bit accesses. all 32-bit accesses are aligned to even address boundaries. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 23 post office box 1443 ? houston, texas 77251 ? 1443 register map (continued) table 6. peripheral frame 2 registers ? name address range size (x16) access type reserved 0x0000 7000 0x0000 700f 16 system control registers 0x0000 7010 0x0000 702f 32 eallow protected reserved 0x0000 7030 0x0000 703f 16 spi-a registers 0x0000 7040 0x0000 704f 16 not eallow protected sci-a registers 0x0000 7050 0x0000 705f 16 not eallow protected reserved 0x0000 7060 0x0000 706f 16 external interrupt registers 0x0000 7070 0x0000 707f 16 not eallow protected reserved 0x0000 7080 0x0000 70bf 64 gpio mux registers 0x0000 70c0 0x0000 70df 32 eallow protected gpio data registers 0x0000 70e0 0x0000 70ff 32 not eallow protected adc registers 0x0000 7100 0x0000 711f 32 not eallow protected reserved 0x0000 7120 0x0000 73ff 736 ev-a registers 0x0000 7400 0x0000 743f 64 not eallow protected reserved 0x0000 7440 0x0000 74ff 192 ev-b registers 0x0000 7500 0x0000 753f 64 not eallow protected reserved 0x0000 7540 0x0000 774f 528 sci registers 0x0000 7750 0x0000 775f 16 not eallow protected reserved 0x0000 7760 0x0000 77ff 160 mcbsp registers 0x0000 7800 0x0000 783f 64 not eallow protected reserved 0x0000 7840 0x0000 7fff 1984 ? peripheral frame 2 only allows 16-bit accesses. all 32-bit accesses are ignored (invalid data may be returned or written). pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 24 post office box 1443 ? houston, texas 77251 ? 1443 device emulation registers these registers are used to control the protection mode of the c28x cpu and to monitor some critical device signals. the registers are defined in table 7. table 7. device emulation registers name address range size (x16) description devicecnf 0x0000 0880 0x0000 0881 2 device configuration register deviceid 0x0000 0882 0x0000 0883 2 device id register protstart 0x0000 0884 1 block protection start address register protrange 0x0000 0885 1 block protection range address register reserved 0x0000 0886 0x0000 09ff 378 table 8. devicecnf register bit definitions bits name type reset decsription 1:0 reserved r/w 1,1 for test only 2 reserved r =0 0 3 vmaps r 0/1 vmap configure status. this indicates the status of vmap. 4 reserved r = 0 0 5 xrs r 0/1 reset input signal status. this is connected directly to the xrs input pin. 6 reserved r = 1 1 7 reserved r/w 0 14:8 reserved r = 0 0:0 15 reserved r/w 0 for test only 16 reserved r = 1 1 17 reserved r = 1 1 18 reserved r = 1 1 19 enprot r/w 1 enable write-read protection mode bit. this bit, when set to 1, will enable write-read protection as specified by the protstart and protrange registers. this bit, when set to 0, disables this protection mode. 31:20 spares r = 0 0 table 9. deviceid register bit definitions bits name type reset decsription 15:0 partid r dependent on device these 16 bits specify the part number of the device as follows: 0x0001: f2810 device 0x0002: f2812 device 31:16 revid r 0x0001 (for first silicon) these 16 bits specify the silicon revision number for the particular part. this number always starts with 0x0001 on the first revision of the silicon and is incremented on any subsequent revisions. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 25 post office box 1443 ? houston, texas 77251 ? 1443 device emulation registers (continued) the protstart and protrange registers set the memory address range for which cpu ? write ? followed by ? read ? operations are protected (operations occur in sequence rather then in their natural pipeline order). this is necessary protection for certain peripheral operations. example: the following lines of code perform a write to register 1 (reg1) location and then the next instruction performs a read from register 2 (reg2) location. on the processor memory bus, with block protection disabled, the read operation will be issued before the write as shown: mov @reg1,al ????? + tbit @reg2,#bit_x ????? |????> read +????> write if block protection is enabled, then the read is stalled until the write occurs as shown: mov @reg1,al ????? + tbit @reg2,#bit_x ??? + | | +????> write +??????> read note: the c28x cpu automatically protects writes followed by reads to the same memory address. the protection mechanism described above is for cases where the address is not the same, but within a given region in memory (as defined by the protstart and porotrange registers). table 10. protstart and protrange registers name address size type reset decsription protstart 0x0000 0884 16 r/w 0x0100 ? the protstart register sets the starting address relative to the 16 most significant bits of the processors lower 22-bit address reach. hence, the smallest resolution is 64 words. protrange 0x0000 0885 16 r/w 0x00ff ? the protrange register sets the block size (from the starting address), starting with 64 words and incrementing by binary multiples (64, 128, 256, 512, 1k, 2k, 4k, 8k, 16k, ...., 2m). ? the default values of these registers on reset are selected to cover the peripheral frame 1, peripheral frame 2, and xintf zone 1 areas of the memory map (address range 0x0000 4000 to 0x0000 8000). pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 26 post office box 1443 ? houston, texas 77251 ? 1443 device emulation registers (continued) table 11. protstart valid values ? register bits start address register value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0000 0000 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 0040 0x0001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x0000 0080 0x0002 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x0000 00c0 0x0003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x003f ff00 0xfffc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0x003f ff40 0xfffd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0x003f ff80 0xfffe 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x003f ffc0 0xffff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? the quickest way to calculate register value is to divide the desired block starting address by 64. table 12. protrange valid values ? register bits block size register value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 64 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 0x0001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 256 0x0003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 512 0x0007 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1k 0x000f 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2k 0x001f 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 4k 0x003f 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 8k 0x007f 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 16k 0x00ff 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 32k 0x01ff 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 64k 0x03ff 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 128k 0x07ff 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 256k 0x0fff 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 512k 0x1fff 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1m 0x3fff 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2m 0x7fff 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4m 0xffff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? not all register values are valid. the protstart address value must be a multiple of the range value. for example: if the block size is set to 4k, then the start address can only be at any 4k boundary. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 27 post office box 1443 ? houston, texas 77251 ? 1443 external interface, xintf (f2812 only) this section gives a top-level view of the external interface (xintf) that is implemented on the f2812 device. the external interface is a non-multiplexed asynchronous bus, similar to the c240x external interface. the external interface on the f2812 is mapped into five fixed zones shown in figure 3. figure 3 shows the f2812 xintf signals. xd(15:0) xa(18:0) xzcs0 xzcs6 xzcs7 xzcs6and7 xzcs1 xzcs2 xwe xrnw xready xmp/mc xhold xholda xclkout (see note d) xrd xintf zone 0 (8k 16) xintf zone 1 (8k 16) xintf zone 6 (1m 16) xintf zone 7 (16k 16) (mapped here if mp/mc =1) 0x0040 ? 0000 0x003f ? c000 0x0020 ? 0000 0x0010 ? 0000 0x0000 ? 6000 0x0000 ? 4000 0x0000 ? 2000 0x0000 ? 0000 data space prog space xintf zone 2 (512k 16) 0x0008 ? 0000 notes: a. the mapping of xintf zone 7 is dependent on the xmp/mc device input signal and the mp/mc mode bit (bit 8 of xintcnf2 register). zones 0, 1, 2, and 6 are always enabled. b. each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects (xzcs0 , xzcs1 , xzcs2 , xzcs6and7 ), which toggle when an access to a particular zone is performed. these features enable glueless connection to many external memories and peripherals. c. the chip selects for zone 6 and 7 are anded internally together to form one chip select (xzcs6and7 ). any external memory that is connected to xzcs6and7 is dually mapped to both zones 6 and zone 7. this means that if zone 7 is disabled (via the mp/mc mode) then any external memory is still accessible via zone 6 address space. d. xclkout is also pinned out on the f2810. figure 3. external interface block diagram pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 28 post office box 1443 ? houston, texas 77251 ? 1443 external interface, xintf (f2812 only) (continued) the operation and timing of the external interface, can be controlled by the registers listed in table 13. table 13. xintf configuration and control register mappings name address size (x16) description xtiming0 0x0000 ? 0b20 2 xintf timing register, zone 0 xtiming1 0x0000 ? 0b22 2 xintf timing register, zone 1 xtiming2 0x0000 ? 0b24 2 xintf timing register, zone 2 xtiming6 0x0000 ? 0b2c 2 xintf timing register, zone 6 xtiming7 0x0000 ? 0b2e 2 xintf timing register, zone 7 xintcnf2 0x0000 ? 0b34 2 xintf configuration register xbank 0x0000 ? 0b38 1 xintf bank control register xrevision 0x0000 ? 0b3a 1 xintf revision register timing registers xintf signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. the timing parameters can be configured individually for each zone. this allows the programmer to maximize the efficiency of the bus, based on the type of memory or peripheral that the user needs to access. all xintf timing values are with respect to xtimclk, which is equal to or one-half of the sysclkout rate, as shown in figure 4. xtiming0 xtiming1 xtiming2 xtiming6 xtiming7 xbank lead/active/trail 1 0 xclkout /2 xtimclk 1 0 /2 c28x cpu xintcnf2 (clkmode) xintcnf2 (xtimclk) default value after reset sysclkout figure 4. relationship between xtimclk and sysclkout pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 29 post office box 1443 ? houston, texas 77251 ? 1443 timing registers (continued) the individual timing parameters can be programmed into the xtiming registers as described in table 14. table 14. xtiming0/1/2/6/7 register bit definitions bit name access reset description 1:0 xwrtrail r/w 1,1 two-bit field that defines the write cycle trail period, in xtimclk cycles, from 0,1,2,3 (if x2timing bit is 0) or 0,2,4,6 (if x2timing bit is 1). 4:2 xwractive r/w 1,1,1 three-bit field that defines the write cycle active wait-state period, in xtimclk cycles, from 0,1,2,3,4,5,6,7 (if x2timing bit is 0) or 0,2,4,6,8,10,12,14 (if x2timing bit is 1). notes: 1. if the useready bit is set to 1 (using xready), then xwractive must be 1. 2. the active period is by default 1 cycle. hence the total active period is 1 + xwractive value. 6:5 xwrlead r/w 1,1 two-bit field that defines the write cycle lead period, in xtimclk cycles, from 1,2,3 (if x2timing bit is 0) or 2,4,6 (if x2timing bit is 1). note: xwrlead must be 1. 8:7 xrdtrail r/w 1,1 two-bit field that defines the read cycle trail period, in xtimclk cycles, from 0,1,2,3 (if x2timing bit is 0) or 0,2,4,6 (if x2timing bit is 1). 11:9 xrdactive r/w 1,1,1 three-bit field that defines the read cycle active wait-state period, in xtimclk cycles, from 0,1,2,3,4,5,6,7 (if x2timing bit is 0) or 0,2,4,6,8,10,12,14 (if x2timing bit is 1). notes: 1. if the useready bit is set to 1 (using xready), then xrdactive must be 1. 2. the active period is by default 1 cycle. hence the total active period is 1 + xrdactive value. 13:12 xrdlead r/w 1,1 two-bit field that defines the read cycle lead period, in xtimclk cycles, from 1,2,3 (if x2timing bit is 0) or 2,4,6 (if x2timing bit is 1). note: xrdlead must be 1. 14 useready r/w 1 when set, the xready signal can be used to further extend the active portion of the cycle past the minimum defined by the xrdactive and xwractive fields. when cleared xready is ignored. 15 readymode r/w 1 when set, the xready input is asynchronous. when cleared, the xready input is synchronous. 17:16 reserved r/w 1,1 reserved. these two bits must always be written to as 1,1. any other combination is reserved and will result in incorrect xintf behavior. 21:18 reserved r 0 reserved 22 x2timing r/w 1 this bit specifies the scaling factor of the lead, active, trail values in the individual timing registers. if this bit is 0, the values are scaled 1:1. if this bit is 1, the values are scaled 2:1 (doubled). the default mode of operation on power up and reset is 2:1 scaling (doubled) mode. 31:23 reserved r 0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 30 post office box 1443 ? houston, texas 77251 ? 1443 timing registers (continued) the minimum timing settings for an xintf access is as follows: when the xready option is not used: the minimum strobe setting is lead = 1, active = 0, trail = 0 hence: l = 0, a = 0,t = 0 settings are not allowed (l = 1, a = 0,t = 0 or l = 1, a = 1,t = 0 or l = 1, a = 0, t = 1 or greater are allowed) when the xready option is used: the minimum strobe setting is lead = 1, active = 1, trail = 0 hence: l = 0, a = 0, t = 0 settings are not allowed (l = 1, a = 1, t = 0 or l = 1, a = 1, t = 1 or greater are allowed). no logic is included to detect illegal settings. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 31 post office box 1443 ? houston, texas 77251 ? 1443 xintcnf2 register table 15. xintcnf2 register bit definitions bits type name reset description 1,0 r/w write buffer depth 0,0 the write buffer allows the processor to continue execution without waiting for xintf write accesses to complete. the write buffer depth is selectable as follows: depth action 00 no write buffering. the cpu will be stalled until the write completes on the xintf. note: default mode on reset (xrs ). 01 the xintf will buffer one word. the cpu is stalled until the write cycle begins on the xintf (there could be a read cycle currently active on the xintf). 10 one write will be buffered without stalling the cpu. the cpu is stalled if a second write follows. the cpu will be stalled until the first write begins its cycle on the xintf. 11 two writes will be buffered without stalling the cpu. the cpu is stalled if a third write follows. the cpu will be stalled until the first write begins its cycle on the xintf. the buffered access can be 8, 16, or 32 bits in length. order of execution is preserved, e.g., writes are performed in the order they were accepted. the processor is stalled on xintf reads until all pending writes are done and the read access completes. if the buffer is full, any pending reads or writes to the buffer will stall the processor. the ? write buffer depth ? can be changed; however, it is recommended that the write buffer depth be changed only when the buffer is empty (this can be checked by reading the ? write buffer level ? bits). writing to these bits when the level is not zero may have unpredictable results. 2 r/w clkmode mode 1 xclkout divide by 2 mode. if this bit is set to 1, xclkout is a divide by 2 of xtimclk. if this bit is set to 0, xclkout is equal to xtimclk. all bus timings, irrespective of which mode is enabled, will start from the rising edge of xclkout. the default mode of operation on power up and reset is /2 mode. 3 r/w clkoff 0 turn xclkout off mode. when this bit is set to 1, the xclkout signal is turned off. this is done for power savings and noise reduction. this bit is set to 0 on a reset. 4 r reserved 1 reserved 5 r reserved 0 reserved pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 32 post office box 1443 ? houston, texas 77251 ? 1443 xintcnf2 register (continued) table 15. xintcnf2 register bit definitions (continued) bits type name reset description 7,6 r wlevel 0,0 the current number of writes buffered are detectable as follows: level action 00 empty 01 1 value currently in the write buffer 10 2 values currently in the write buffer 11 3 values currently in the write buffer the value in the write buffer may be 8-, 16-, or 32-bit data. note : there may be a few cycle delay from when a value enters the write buffer to the buffer level depth being updated. 8 r/w mp/mc mode on reset, this bit reflects the state of the xmp/mc input signal sampled at xrs . the user can modify the state of this bit by writing a 1 or a 0 to this location. this will be reflected on the xmp/mc output signal. this mode also affects zone 7 and boot rom mapping as follows: mp/mc = 1, microprocessor state (xintf zone 7 enabled, boot rom disabled). mp/mc = 0, microcomputer state (xintf zone 7 disabled, boot rom enabled). note : the xmp/mc input signal state is ignored after reset. 9 r/w hold 0 this bit, when low, will automatically grant a request to an external device driving the xhold input signal low (xholda output signal is driven low when request granted). this bit, when set high, will not automatically grant a request to an external device driving the xhold input signal low (xholda output signal stays high). if this bit is set, while xhold and xholda are both low (external bus accesses granted) then the xholda signal is forced high (at the end of the current cycle) and the exteranl interface is taken out of high-impedance mode. on a reset xrs , this bit is set to zero. if on a reset the xhold signal is active-low, then the bus and all signal strobes must be in high-impedance state and the xholda signal also driven active-low. when hold mode is enabled and xholda is active-low (external bus grant active) then the core can still execute code from internal memory. if an access is made to the external interface, then a not ready signal is generated and the core is stalled until the xhold signal is removed. 10 r holds xhold input signal this bit reflects the current state of the xhold input signal. it can be read by the user to determine if an external device is requesting access to the external bus. 11 r holdas xholda input signal this bit reflects the current state of the xholda output signal. it can be read by the user to determine if the external interface is currently granting access to an external device. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 33 post office box 1443 ? houston, texas 77251 ? 1443 xintcnf2 register (continued) table 15. xintcnf2 register bit definitions (continued) bits type name reset description 15:12 x reserved 0 reserved 18:16 r/w xtimclk 0,0,1 these bits select the fundamental clock for the timing of lead, active and trail switching operations as defined by the xtiming and xbank registers: mode action 0,0,0 xtimclk = sysclkout/1 0,0,1 xtimclk = sysclkout/2 0,1,0 reserved 0,1,1 reserved 1,0,0 reserved 1,0,1 reserved 1,1,0 reserved 1,1,1 reserved xbank register table 16. xbank register bit defintions bits type name reset description 2:0 r/w bank 1,1,1 these bits specify the xintf zone for which bank switching is enabled, zone 0 to zone 7. at reset, xintf zone 7 is selected. 5:3 r/w bcyc 1,1,1 these bits specify the number of xtimclk cycles to add between any consecutive access that crosses into or out of the specified zone, be it a read or write, program or data space. the number of xtimclk cycles can be 0 to 14. on a reset (xrs ) the value defaults to 14 cycles. 14:6 x reserved 15 r/w reserved 1 xrevision register the xrevision register contains a unique number to identify the particular version of xintf used in the product. for the f2812, this register will be configured as described in table 17. table 17. xrevision register bit defintions bit(s) name type reset description 15 ? 0 revision r 0x0004 current xintf revision. for internal use/reference. test purposes only. subject to change. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 34 post office box 1443 ? houston, texas 77251 ? 1443 interrupts figure 5 shows how the various interrupt sources are multiplexed within the f2810 and f2812 devices. c28x cpu pie timer 2 (for rtos) timer 0 watchdog peripherals (spi, sci, mcbsp, can, ev, adc) (41 interrupts) 96 interrupts ? tint0 interrupt control xnmicr(15:0) xint1 interrupt control xint1cr(15:0) xint2 interrupt control xint2cr(15:0) gpio mux wdint int1 to int12 int13 int14 nmi xint1ctr(15:0) xint2ctr(15:0) xnmictr(15:0) timer 1 (for rtos) tint2 low-power modes lpmint wakeint xnmi_xint13 mux tint1 enable select ? out of a possible 96 interrupts, 45 are currently used by peripherals. figure 5. interrupt sources pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 35 post office box 1443 ? houston, texas 77251 ? 1443 interrupts (continued) eight pie block interrupts are grouped into one cpu interrupt. in total, 12 cpu interrupt groups, with 8 interrupts per group equals 96 possible interrupts. on the f2810/f2812, 45 of these are used by peripherals as shown in table 18. int12 mux int11 int2 int1 cpu (enable) (flag) intx intx.8 pieierx(7:1) pieifrx(7:1) mux intx.7 intx.6 intx.5 intx.4 intx.3 intx.2 intx.1 from peripherals or external interrupts (enable) (flag) ier(12:1) ifr(12:1) global enable intm 1 0 figure 6. multiplexing of interrupts using the pie block table 18. pie peripheral interrupts ? cpu pie interrupts cpu interrupts intx.1 intx.2 intx.3 intx.4 intx.5 intx.6 intx.7 intx.8 int1 pdpinta (ev-a) pdpintb (ev-b) reserved xint1 xint2 adcint (adc) tint0 (timer 0) wakeint (lpm/wd) int2 cmp1int (ev-a) cmp2int (ev-a) cmp3int (ev-a) t1pint (ev-a) t1cint (ev-a) t1ufint (ev-a) t1ofint (ev-a) reserved int3 t2pint (ev-a) t2cint (ev-a) t2ufint (ev-a) t2ofint (ev-a) capint1 (ev-a) capint2 (ev-a) capint3 (ev-a) reserved int4 cmp4int (ev-b) cmp5int (ev-b) cmp6int (ev-b) t3pint (ev-b) t3cint (ev-b) t3ufint (ev-b) t3ofint (ev-b) reserved int5 t4pint (ev-b) t4cint (ev-b) t4ufint (ev-b) t4ofint (ev-b) capint4 (ev-b) capint5 (ev-b) capint6 (ev-b) reserved int6 spiaint (spi) spiatx (spi) reserved reserved mrint (mcbsp) mxint (mcbsp) reserved reserved int7 reserved reserved reserved reserved reserved reserved reserved reserved int8 reserved reserved reserved reserved reserved reserved reserved reserved int9 rxaint (sci-a) txaint (sci-a) rxbint (sci-b) txbint (sci-b) hecc0int (can) hecc1int (can) reserved reserved int10 reserved reserved reserved reserved reserved reserved reserved reserved int11 reserved reserved reserved reserved reserved reserved reserved reserved int12 reserved reserved reserved reserved reserved reserved reserved reserved ? out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. however, these interrupts can be used as software interrupts if they are enabled at the pieifrx level. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 36 post office box 1443 ? houston, texas 77251 ? 1443 vector table mapping the interrupt vector table can be mapped into the five distinct areas listed in table 19. table 19. interrupt vector table mapping ? vector maps vectors fetched from address range vmap m0m1map mp/mc enpie m1 vector ? m1 saram block 0x000000 ? 0x00003f 0 0 x x m0 vector m0 saram block 0x000000 ? 0x00003f 0 1 x x brom vector rom block 0x3fffc0 ? 0x3fffff 1 x 0 0 xintf vector xintf zone 7 block 0x3fffc0 ? 0x3fffff 1 x 1 0 pie vector pie block 0x000d00 ? 0x000dff 1 x x 1 ? on the f2810 and f2812 devices, the vmap and m0m1map modes are set to ? 1 ? on reset. the enpie mode is forced to ? 0 ? on reset. ? vector map m1 vector is a reserved mode only. valid on f2812 only after reset operation, the vector table will be located in the areas listed in table 20. table 20. vector table mapping after reset operation ? vector maps reset fetched from address range vmap m0m1map mp/mc enpie brom vector rom block 0x3fffc0 ? 0x3fffff 1 1 0 0 xintf vector xintf zone 7 block 0x3fffc0 ? 0x3fffff 1 1 1 0 ? on the f2810 and f2812 devices, the vmap and m0m1map modes are set to ? 1 ? on reset. the enpie mode is forced to ? 0 ? on reset. valid on f2812 only the vector mapping is controlled by the following mode bits/signals: vmap: this bit is found in status register 1 (bit 3). a device reset sets this bit to 1. the state of this bit can be modified by writing to st1 or by ? setc/clrc vmap ? instructions. m0m1map: this bit is found in status register 1 (bit 11). a device reset sets this bit to 1. the state of this bit can be modified by writing to st1 or by ? setc/clrc m0m1map ? instructions. this bit should remain set. m0m1map = 0 is reserved for ti testing. mp/mc : this bit is found in xintcnf2 register (bit 8). on the f2812, the default value of this bit, on reset, is set by the xmp/mc input device signal. on the f2810, xmp/mc is tied low internally. the state of this bit can be modified by writing to the xintcnf2 register (address 0x0000 0b34). enpie: this bit is found in piectrl register (bit 0). the default value of this bit, on reset, is set to ? 0 ? (pie disabled). the state of this bit can be modified by writing to the piectrl register (address 0x0000 0ce0). the external interrupts are configured using the registers listed in table 27. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 37 post office box 1443 ? houston, texas 77251 ? 1443 vector table mapping (continued) reset (power-on reset or warm reset) pie disabled (enpie = 0) vmap = 1 objmode = 0 amode = 0 m0m1map = 1 xmp/mc input signal = 0? ? (f2812 only) reset vector fetched from xintf vector map reset vector fetched from boot rom branch into bootloader routines depending on the state of gpio pins using peripheral interrupts? vmap = 1? (f2812 only) vectors (except for reset) will be fetched from xintf vector map vectors (except for reset) will be fetched from brom vector map mp/mc status bit = 0? ? vectors (except for reset) will be fetched from pie vector map no yes no yes no yes no yes vectors (except for reset) will be fetched from m0 vector map ? the xmp/mc input signal is tied low internally on the f2810. ? the compatibility operating mode of the f2810 and f2812 is determined by a combination of the objmode and amode bits in status register 1 (st1): operating mode objmode amode c28x mode 1 0 c2xlp source-compatible 1 1 c27x object-compatible 0 0 (default at reset) the reset vector is always fetched from either the brom or xintf vector map depending on the xmp/mc input signal. ? the state of the xmp/mc signal is latched into the mp/mc bit at reset, it can then be modified by software. recommended flow for f2810/f2812 applications used for test purposes only user code initializes: objmode and amode state ? pie enable (enpie = 1) pie vector table pieierx registers cpu ier register and intm user code initializes: objmode and amode state ? cpu ier register and intm vmap state mp/mc status bit ? figure 7. reset flow diagram pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 38 post office box 1443 ? houston, texas 77251 ? 1443 pie vector map the pie vector table (table 21) consists of a 256 x 16 saram that can also be used as ram if the pie block is not in use. the pie vector table contents are undefined on reset. interrupt priority for int1 to int12 is fixed by the cpu. priority for each group of 8 interrupts is, controlled by the pie. for example: if int1.1 should occur simultaneously with int8.1, both interrupts will be presented to the cpu simultaneously by the pie block, and the cpu will service int1.1 first. if int1.1 should occur simultaneously with int1.8, then int1.1 will be sent to the cpu first and then int1.8 will follow. interrupt prioritization is performed during the vector fetch portion of the interrupt processing. a ? trap 1 ? to ? trap 12 ? instruction or an ? intr int1 ? to ? intr int12 ? instruction will always fetch the vector from the first location of each group ( ? intr1.1 ? to ? int12.1 ? ). hence, it is recommended that these instructions not be used when pie is enabled. the ? trap 0 ? operation will fetch the vector from location 0x0000 0d00. the vector table is eallow protected. table 21. pie vector table name address size (x16) description core priority pie group priority not used 0x0000 0d00 2 reset never fetched here 1 (highest) ? not used 0x0000 0d02 2 int1 remapped to int1.1 ? int1.8 below ? ? not used 0x0000 0d04 2 int2 remapped to int2.1 ? int2.8 below ? ? not used 0x0000 0d06 2 int3 remapped below ? ? not used 0x0000 0d08 2 int4 remapped below ? ? not used 0x0000 0d0a 2 int5 remapped below ? ? not used 0x0000 0d0c 2 int6 remapped below ? ? not used 0x0000 0d0e 2 int7 remapped below ? ? not used 0x0000 0d10 2 int8 remapped below ? ? not used 0x0000 0d12 2 int9 remapped below ? ? not used 0x0000 0d14 2 int10 remapped below ? ? not used 0x0000 0d16 2 int11 remapped below ? ? not used 0x0000 0d18 2 int12 remapped below ? ? int13 0x0000 0d1a 2 external interrupt 13 (xint13) or cpu-timer 1 (for rtos use) 17 ? int14 0x0000 0d1c 2 cpu-timer 2 (for rtos use) 18 ? datalog 0x0000 0d1e 2 cpu data logging interrupt 19 (lowest) ? rtosint 0x0000 0d20 2 cpu real-time os interrupt 4 ? emuint 0x0000 0d22 2 cpu emulation interrupt 2 ? nmi 0x0000 0d24 2 external non-maskable interrupt 3 ? illegal 0x0000 0d26 2 illegal operation ? ? user0 0x0000 0d28 2 user defined trap ? ? . . . . . . user11 0x0000 0d3e 2 user defined trap ? ? int1.1 0x0000 0d40 2 1 (highest) . . . group 1 interrupt vectors 5 . int1.8 0x0000 0d4e 2 grou 1 interru t vectors 5 8 (lowest) . . . . . . . . . group 2 interrupt vectors to group 11 interrupt vectors 6 to 15 int12.1 0x0000 0df0 2 1 (highest) . . . group 12 interrupt vectors 16 . int12.8 0x0000 0dfe 2 grou 12 interru t vectors 16 8 (lowest) pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 39 post office box 1443 ? houston, texas 77251 ? 1443 pie registers the registers controlling the functionality of the pie block are listed in table 22. table 22. pie configurations and control register mappings ? name address size (x16) description piectrl 0x0000 ? 0ce0 1 pie, control register pieack 0x0000 ? 0ce1 1 pie, acknowledge register pieier1 0x0000 ? 0ce2 1 pie, int1 group enable register pieifr1 0x0000 ? 0ce3 1 pie, int1 group flag register pieier2 0x0000 ? 0ce4 1 pie, int2 group enable register pieifr2 0x0000 ? 0ce5 1 pie, int2 group flag register pieier3 0x0000 ? 0ce6 1 pie, int3 group enable register pieifr3 0x0000 ? 0ce7 1 pie, int3 group flag register pieier4 0x0000 ? 0ce8 1 pie, int4 group enable register pieifr4 0x0000 ? 0ce9 1 pie, int4 group flag register pieier5 0x0000 ? 0cea 1 pie, int5 group enable register pieifr5 0x0000 ? 0ceb 1 pie, int5 group flag register pieier6 0x0000 ? 0cec 1 pie, int6 group enable register pieifr6 0x0000 ? 0ced 1 pie, int6 group flag register pieier7 0x0000 ? 0cee 1 pie, int7 group enable register pieifr7 0x0000 ? 0cef 1 pie, int7 group flag register pieier8 0x0000 ? 0cf0 1 pie, int8 group enable register pieifr8 0x0000 ? 0cf1 1 pie, int8 group flag register pieier9 0x0000 ? 0cf2 1 pie, int9 group enable register pieifr9 0x0000 ? 0cf3 1 pie, int9 group flag register pieier10 0x0000 ? 0cf4 1 pie, int10 group enable register pieifr10 0x0000 ? 0cf5 1 pie, int10 group flag register pieier11 0x0000 ? 0cf6 1 pie, int11 group enable register pieifr11 0x0000 ? 0cf7 1 pie, int11 group flag register pieier12 0x0000 ? 0cf8 1 pie, int12 group enable register pieifr12 0x0000 ? 0cf9 1 pie, int12 group flag register reserved 0x0000 ? 0cfa 0x0000 ? 0cff 6 reserved ? the pie configuration and control registers are not protected by eallow mode. the pie vector table is protected. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 40 post office box 1443 ? houston, texas 77251 ? 1443 pie registers (continued) table 23. piectrl register bit definitions bit(s) name type reset description 0 enpie r/w 0 enable vector fetching from pie block. when this bit is set to 1, all vectors are fetched from the pie vector table. if this bit is set to 0, the pie block is disabled and vectors are fetched as normal. all pie block registers (pieack, pieifr, pieier) can be accessed even when the pie block is disabled. 15:1 pievect r 0 vector fetch address. displays the address of the vector that was fetched. the least significant bit of the address is ignored and only bits 1 to 15 are shown. the vector address can be used to determine which interrupt generated the fetch. table 24. pieack register bit definitions bit(s) name type reset description 11:0 pieack r/w=1 0 writing a 1 to the respective interrupt bit enables the pie block to drive a pulse into the cpu interrupts input, if an interrupt is pending on any of the group interrupts. reading this register indicates if an interrupt is pending in the respective group. bit 0 refers to int1 up to bit 11, which refers to int12. note: writes of 0 are ignored. 15:12 spares r=0 0 table 25. pieierx register bit definitions ? bit(s) name type reset description 0 intx.1 r/w 0 1 intx.2 r/w 0 2 intx.3 r/w 0 3 intx.4 r/w 0 these register bits individually enable an interru p t within a grou p they behave very much 4 intx.5 r/w 0 th ese reg i s t er bit s i n di v id ua ll y ena bl e an i n t errup t w ithi n a group. th ey b e h ave very muc h like the cpu interrupt enable register. setting a bit to 1 will enable the servicing of the 5 intx.6 r/w 0 like the cpu interru t enable register . setting a bit to 1 will enable the servicing of the respective interrupt. setting a bit to 0 will disable the servicing of the bit. 6 intx.7 r/w 0 7 intx.8 r/w 0 15:8 spares r=0 0 ? x = 1 to 12. intx means cpu interrupts int1 to int12. table 26. pieifrx register bit definitions ? bit(s) name type reset description 0 intx.1 r/w 0 1 intx.2 r/w 0 2 intx.3 r/w 0 these register bits indicate if an interrupt is currently active. they behave very much like th cpu i t t fl i t wh i t t i ti th ti i t bit i t 3 intx.4 r/w 0 the cpu interrupt flag register. when an interrupt is active, the respective register bit is set. the bit is cleared when the interru p t is serviced or by writing a 0 to the register bit this 4 intx.5 r/w 0 the bit is cleared w hen the interr u pt is ser v iced or b y w riting a 0 to the register bit . this register can also be read to determine which interrupts are active or pending. 5 intx.6 r/w 0 register can also be read to determine which interru ts are active or ending. note: the pieifr register bit is cleared during the interrupt vector fetch portion of 6 intx.7 r/w 0 note: the pieifr register bit is cleared during the interrupt vector fetch portion of the interru p t p rocessing. 7 intx.8 r/w 0 the interrupt processing . 15:8 spares r=0 0 ? x = 1 to 12. intx means cpu interrupts int1 to int12. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 41 post office box 1443 ? houston, texas 77251 ? 1443 pie/cpu interrupt response figure 8 shows the behavior of the pie hardware under various pieifr and pieier register conditions. there is one pieack bit for every cpu interrupt group (int1 to int12) and is referred to as pieack(x). there is a corresponding pieifr and pieier register for each group and are referred to as the pieifrx and pieierx registers. figure 8 describes the operation of one pie interrupt. this flow is common to all pie interrupts. start stage a pieifrx.y = 1 stage b pieierx.y = 1 stage c pieackx = 0 yes yes yes wait for s/w to clear pieackx bit = 0 wait for pieierx.y = 1 wait for any pieifrx.y = 1 stage d interrupt request sent to 28x cpu on intx stage e ifrx bit set 1 interrupts to cpu stage f ierx bit = 1 stage g intm bit = 0 stage h cpu responds branches to vector address at pieifrx.y ifrx bit cleared context save ier = 0 intm = 1 pieifrx.y bit cleared stage i interrupt service routine responds write 1 to pieackx bit to clear to enable other interrupts in pieifrx group re-enable interrupts, intm = 0 return yes yes no wait for ierx = 1 wait for intm = 0 end vector branch interrupt service routine (isr) for pieifrx.y pie interrupt control cpu interrupt control no no no no figure 8. typical pie/cpu interrupt response ? intx.y pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 42 post office box 1443 ? houston, texas 77251 ? 1443 external interrupts table 27. external interrupts registers name address range size (x16) description xint1cr 0x0000 7070 1 xint1 configuration register xint2cr 0x0000 7071 1 xint2 configuration register reserved 0x0000 7072 0x0000 7076 5 xnmicr 0x0000 7077 1 xnmi configuration register xint1ctr 0x0000 7078 1 xint1 counter register xint2ctr 0x0000 7079 1 xint2 counter register reserved 0x0000 707a 0x0000 707e 5 xnmictr 0x0000 707f 1 xnmi counter register each external interrupt can be enabled/disabled or qualified using positive or negative going edge. the register bits to control this are described in table 28. table 28. xint1/2cr register bit definitions bits name type reset description 0 enable r/w 0 0 interrupt disabled 1 interrupt enabled 1 reserved r = 0 0 2 polarity r/w 0 0 interrupt is selected as negative edge triggered 1 interrupt is selected as positive edge triggered 15:3 reserved r = 0 0:0 table 29 shows the bit definitions of the xnmicr register. table 29. xnmicr register bit definitions bits name type reset description 0 enable r/w 0 0 nmi interrupt disabled 1 nmi interrupt enabled 1 select r/w 0 0 timer 1 connected to int13 1 xnmi connected to int13 2 polarity r/w 0 0 interrupt is selected as negative edge triggered 1 interrupt is selected as positive edge triggered 15:3 reserved r = 0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 43 post office box 1443 ? houston, texas 77251 ? 1443 external interrupts (continued) the masked interrupts, xint1/2 and nmi, also contain a 16-bit up-counter register that is reset to 0x0000 whenever an interrupt edge is detected. this counter can be used to accurately time stamp the occurrence of the interrupt. table 30 shows the bit definitions of the xint1/2ctr and xnmictr registers. table 30. xint1/2ctr and xnmictr registers bit definitions bits name type reset description 15:0 intctr r 0:0 this is a free running 16-bit up-counter that is clocked at the sysclkout rate. the counter value is reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid interrupt edge is detected. the counter must only be reset by the selected polarity edge as selected in the respective interrupt control register. when the interrupt is disabled, the counter will stop. the counter is a free-running counter and will wrap around to zero when the max value is reached. the counter is a read only register and can only be reset to zero by a valid interrupt edge or by reset. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 44 post office box 1443 ? houston, texas 77251 ? 1443 system control this section describes the f2810 and f2812 oscillator, pll and clocking mechanisms, the watchdog function and the low power modes. figure 9 shows the various clock and reset domains in the f2810 and f2812 devices that will be discussed. hspclk pll x1/xclkin x2 power modes control watchdog block c28x cpu peripheral bus low-speed peripherals sci-a/b, spi, mcbsp peripheral registers high-speed peripherals ev-a/b high-speed prescaler low-speed prescaler clock enables gpio mux system control registers peripheral registers xplldis adc registers 12-bit adc 16 adc inputs hspclk lspclk i/o i/o peripheral reset sysclkout xrs reset gpios ecan peripheral registers i/o osc clkin figure 9. clock and reset domains pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 45 post office box 1443 ? houston, texas 77251 ? 1443 system control (continued) the pll, clocking, watchdog and low-power modes, are controlled by the registers listed in table 31. table 31. pll, clocking, watchdog, and low-power mode registers ? name address size (x16) description reserved 0x0000 ? 7010 0x0000 ? 7017 8 reserved 0x0000 ? 7018 1 reserved 0x0000 ? 7019 1 hispcp 0x0000 ? 701a 1 high-speed peripheral clock prescaler register for hspclk clock lospcp 0x0000 ? 701b 1 low-speed peripheral clock prescaler register for hspclk clock pclkcr 0x0000 ? 701c 1 peripheral clock control register reserved 0x0000 ? 701d 1 lpmcr0 0x0000 ? 701e 1 low power mode control register 0 lpmcr1 0x0000 ? 701f 1 low power mode control register 1 reserved 0x0000 ? 7020 1 pllcr 0x0000 ? 7021 1 pll control register ? scsr 0x0000 ? 7022 1 system control & status register wdcntr 0x0000 ? 7023 1 watchdog counter register reserved 0x0000 ? 7024 1 wdkey 0x0000 ? 7025 1 watchdog reset key register reserved 0x0000 ? 7026 0x0000 ? 7028 3 wdcr 0x0000 ? 7029 1 watchdog control register reserved 0x0000 ? 702a 0x0000 ? 702f 6 ? all of the above registers can only be accessed, by executing the eallow instruction. ? the pll control register (pllcr) is reset to a known state by the xrs signal only. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 46 post office box 1443 ? houston, texas 77251 ? 1443 system control (continued) the pclkcr1 and pclkcr2 registers basically enable/disable clocks to the various peripheral modules in the f2810 and f2812 devices. table 32 lists the bit descriptions of the pclkcr1 and pclkcr2 registers. table 32. pclkcr register bit definitions ? bit(s) name type reset description 0 evaenclk r/w 0 if this bit is set, it enables the high-speed clock (hspclk) within the ev-a peripheral. for low power operation, this bit is set to zero by the user or by reset. 1 evbenclk r/w 0 if this bit is set, it enables the high-speed clock (hspclk) within the ev-b peripheral. for low power operation, this bit is set to zero by the user or by reset. 2 reserved r=0 0 reserved 3 adcenclk r/w 0 if this bit is set, it enables the high-speed clock (hspclk) within the adc peripheral. for low power operation, this bit is set to zero by the user or by reset. 7:4 reserved r=0 0:0 8 spiaenclk r/w 0 if this bit is set, it enables the low-speed clock (lspclk) within the spi peripheral. for low power operation, this bit is set to zero by the user or by reset. 9 reserved r=0 0 reserved 10 sciaenclk r/w 0 if this bit is set, it enables the low-speed clock (lspclk) within the sci-a peripheral. for low power operation, this bit is set to zero by the user or by reset. 11 scibenclk r/w 0 if this bit is set, it enables the low-speed clock (lspclk) within the sci-b peripheral. for low power operation, this bit is set to zero by the user or by reset. 12 maenclk r/w 0 if this bit is set, it enables the low-speed clock (lspclk) within the mcbsp peripheral. for low power operation, this bit is set to zero by the user or by reset. 13 reserved r=0 0 reserved 14 heccaenclk r/w 0 if this bit is set, it enables the system clock within the can peripheral. for low power operation, this bit is set to zero by the user or by reset. 15 reserved r=0 0 reserved ? if a peripheral block is not used, then the clock to that peripheral can be turned off to minimize power consumption. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 47 post office box 1443 ? houston, texas 77251 ? 1443 system control (continued) the system control and status register contains the watchdog override bit and the watchdog interrupt enable/disable bit. table 33 describes the bit functions of the scsr register. table 33. scsr register bit definitions bit(s) name type reset description 0 wdoverride r/w=1 1 if this bit is set to 1, the user is allowed to change the state of the watchdog disable (wddis) bit in the watchdog control (wdcr) register (refer to watchdog block section of this data sheet). if the wdoverride bit is cleared, by writing a 1 the wddis bit cannot be modified by the user. writing a 0 will have no effect. if this bit is cleared, then it will remain in this state until a reset occurs. the current state of this bit is readable by the user. 1 wdenint r/w 0 if this bit is set to 1, the watchdog reset (wdrst ) output signal is disabled and the watchdog interrupt (wdint ) output signal is enabled. if this bit is zero, then the wdrst output signal is enabled and the wdint output signal is disabled. this is the default state on reset (xrs ). 15:2 reserved r=0 0:0 the hispcp and lospcp registers are used to configure the high- and low-speed peripheral clocks, respectively. see table 34 for the hispcp bit definitions and table 35 for the lospcp bit definitions. table 34. hispcp register bit definitions bit(s) name type reset description 2:0 hspclk r/w 0,0,1 these bits configure the high-speed peripheral clock (hspclk) rate relative to sysclkout: 000 hspclk = sysclkout / 1 001 hspclk = sysclkout / 2 010 hspclk = sysclkout / 4 011 hspclk = sysclkout / 6 100 hspclk = sysclkout / 8 101 hspclk = sysclkout / 10 110 hspclk = sysclkout / 12 111 hspclk = sysclkout / 14 hspclk = sysclkout / (hspclk x 2) = sysclkout if hispcp value is zero 15:3 reserved r=0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 48 post office box 1443 ? houston, texas 77251 ? 1443 system control (continued) table 35. lospcp register bit definitions bit(s) name type reset description 2:0 lspclk r/w 0,1,0 these bits configure the low-speed peripheral clock (lspclk) rate relative to sysclkout: 000 lspclk = sysclkout / 1 001 lspclk = sysclkout / 2 010 lspclk = sysclkout / 4 011 lspclk = sysclkout / 6 100 lspclk = sysclkout / 8 101 lspclk = sysclkout / 10 110 lspclk = sysclkout / 12 111 lspclk = sysclkout / 14 lspclk = sysclkout / (lspclk x 2) = sysclkout if lospcp value is zero 15:3 reserved r=0 0:0 note: the hspclk is set to sysclkout/2 and lspclk is set to sysclkout/4 on reset. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 49 post office box 1443 ? houston, texas 77251 ? 1443 osc and pll block the osc and pll block on the f2810 and f2812 will use a zero-pin phase-locked loop (zpll). figure 10 shows the implemented features and relevant signals. xtal2 xtal1/clkin on-chip oscillator (osc) 4-bit pll select pll bypass /2 xplldis pll oscclk figure 10. osc and pll block the osc circuit enables a crystal to be attached to the f2810 and f2812 devices using the x1 and x2 pins. if a crystal is not used, then an external oscillator can be directly connected to the xclkin pin and the x2 pin is left unconnected. the oscillator input range is 20 mhz to 35 mhz. table 36. pllcr register bit definitions bit(s) name type xrs reset ? description 3:0 div r/w 0,0,0,0 these bits set the pll clocking ratio. the range of values should be between (x 1.0) to (x 10.0). the scale between these values should be as linear as possible: 0000 x 0.5 pll bypassed but enabled clkin = oscclk / 2 0001 x 1.0 pll connected clkin (oscclk * 1.0) / 2 0010 x 2.0 clkin = (oscclk * 2.0) / 2 0011 x 3.0 clkin = (oscclk * 3.0) / 2 0100 x 4.0 clkin = (oscclk * 4.0) / 2 0101 x 5.0 clkin = (oscclk * 5.0) / 2 0110 x 6.0 clkin = (oscclk * 6.0) / 2 0111 x 7.0 clkin = (oscclk * 7.0) / 2 1000 x 8.0 clkin = (oscclk * 8.0) / 2 1001 x 9.0 clkin = (oscclk * 9.0) / 2 1010 x 10.0 clkin = (oscclk * 10.0) / 2 1011 spare 1100 spare 1101 spare 1110 spare 1111 spare 15:4 reserved r=0 0:0 ? the pllcr register is reset to a known state by the xrs reset line. if a reset is issued by the debugger, the pll clocking ratio is not changed. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 50 post office box 1443 ? houston, texas 77251 ? 1443 pll-based clock module the f2810 and f2812 have an on-chip, pll-based clock module. this module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. the pll has a 4-bit ratio control to select different cpu clock rates. the pll-based clock module provides two modes of operation: crystal-operation this mode allows the use of an external crystal/resonator to provide the time base to the device. external clock source operation this mode allows the internal oscillator to be bypassed. the device clocks are generated from an external clock source input on the xtal1/clkin pin. in this case, an external oscillator clock is connected to the xtal1/clkin pin. external reference oscillator clock option ti recommends that customers have the resonator/crystal vendor characterize the operation of their device with the dsp chip. the resonator/crystal vendor has the equipment and expertise to tune the tank circuit. the vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 51 post office box 1443 ? houston, texas 77251 ? 1443 watchdog block the watchdog block on the f2810 and f2812 is identical to the one used on the 240x devices. the watchdog module generates an output pulse, 512 oscillator clocks wide (oscclk), whenever the 8-bit watchdog up counter has reached its maximum value. to prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xaa sequence into the watchdog key register which will reset the watchdog counter. figure 11 shows the various functional blocks within the watchdog module. /512 oscclk wdcr (wdps(2:0)) wdclk wdcntr(7:0) wdkey(7:0) bad key good key 1 0 1 wdcr (wdchk(2:0)) bad wdchk key wdcr (wddis) clear counter scsr (wdenint) watchdog prescaler generate output pulse (512 oscclks) 8-bit watchdog counter clr wdrst wdint watchdog 55 + aa key detector xrs xppldis wdrst o.c. note a: the wdrst signal is driven low for 512 oscclk cycles (similarly for the wdint signal if enabled). figure 11. watchdog module the wdint signal enables the watchdog to be used as a wakeup from idle/standby mode timer. in standby mode, all peripherals are turned off on the device. the only peripheral that remains functional is the watchdog. the watchdog module will run off the pll clock or the oscillator clock. the wdint signal is fed to the lpm block so that it can wake the device from standby (if enabled). refer to ? low-power modes block ? section of this data sheet for more details. in idle mode, the wdint signal can generate an interrupt to the cpu, via the pie, to take the cpu out of idle mode. in halt mode, this feature cannot be used because the oscillator (and pll) are turned off and hence so is the watchdog. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 52 post office box 1443 ? houston, texas 77251 ? 1443 watchdog block (continued) table 37. wdcntr register bit definitions bit(s) name type reset description 7:0 wdcntr r/w 0:0 these bits contain the current value of the wd counter. the 8-bit counter continually increments at the wdclk rate. if the counter overflows, then the watchdog initiates a reset. if the wdkey register is written with a valid combination, then the counter is reset to zero. 15:8 reserved r=0 0:0 table 38. wdkey register bit definitions bit(s) name type reset description 7:0 wdkey w/r=0 0:0 writing 0x55 followed by 0xaa will cause the wdcntr bits to be cleared. writing any other value will cause an immediate watchdog reset to be generated. 15:8 reserved r=0 0:0 table 39. wdcr register bit definitions bit(s) name type reset description 2:0 wdps(2:0) r/w 0:0 these bits configure the watchdog counter clock (wdclk) rate relative to oscclk/512: 000 wdclk = oscclk/512/1 001 wdclk = oscclk/512/1 010 wdclk = oscclk/512/2 011 wdclk = oscclk/512/4 100 wdclk = oscclk/512/8 101 wdclk = oscclk/512/16 110 wdclk = oscclk/512/32 111 wdclk = oscclk/512/64 5:3 wdchk(2:0) w/r=0 0:0 the user must always write ? 1,0,1 ? to these bits whenever a write to this register is performed. writing any other value will cause an immediate reset to the core (if wd enabled). 6 wddis r/w 0 writing a 1 to this bit will disable the watchdog module. writing a 0 will enable the module. this bit can only be modified if the wdoverride bit in the scsr2 register is set to 1. on reset, the watchdog module is enabled. 7 wdflag r/w=1 watchdog reset status flag bit. this bit, if set, indicates a watchdog reset (wdrst ) generated the reset condition. if 0, then it was an external device or power-up reset condition. this bit remains latched until the user writes a 1 to clear the condition. writes of 0 will be ignored. 15:8 reserved r=0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 53 post office box 1443 ? houston, texas 77251 ? 1443 watchdog block (continued) when the xrs line is low, the wdflag bit is forced low. the wdflag bit will only be set if a rising edge on wdrst signal is detected (after synch and a 4 cycle delay) and the xrs signal is high. if the xrs signal is low when wdrst goes high, then the wdflag bit will remain at 0. in a typical application, the wdrst signal will connect to the xrs input. hence to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then the watchdog pulse. emulation considerations the watchdog module behaves as follows under various debug conditions: cpu suspended: when the cpu is suspended, the watchdog clock (wdclk) is suspended. run-free mode: when the cpu is placed in run-free mode, then the watchdog module resumes operation as normal. real-time single-step mode: when the cpu is in real-time single-step mode, the watchdog clock (wdclk) is suspended. the watchdog remains suspended even within real-time interrupts. real-time run-free mode: when the cpu is in real-time run-free mode, the watchdog operates as normal. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 54 post office box 1443 ? houston, texas 77251 ? 1443 low-power modes block the low-power modes on the f2810 and f2812 are similar to the 240x devices. table 40 summarizes the various modes. table 40. f2810 and f2812 low-power modes mode idles lpm(1:0) oscclk clkin sysclkout exit ? normal low x,x on on on ? idle high 0,0 on on on ? xrs , wdint , any enabled interrupt, xnmi standby high 0,1 on (watchdog still running) off off xrs , wdint , xint1 , xnmi , t1/2/3/4ctrip , c1/2/3/4/5/6trip , scirxda, scirxdb, canrx, debugger halt high 1,x off (oscillator and pll turned off, watchdog not functional) off off xrs , xnmi , debugger ? the exit column lists which signals or under what conditions the low power mode will be exited. a low signal, on any of the sig nals, will exit the low power condition. this signal must be kept low long enough for an interrupt to be recognized by the device. otherwise the id le mode will not be exited and the device will go back into the indicated low power mode. ? the idle mode on the c28x behaves differently than on the 24x/240x. on the c28x, the clock output from the core (sysclkout) is still functional while on the 24x/240x the clock is turned off. on the c28x, the jtag port can still function even if the core clock (clkin) is turned off. the various low-power modes operate as follows: idle mode: this mode is, exited by any enabled interrupt or an nmi that is recognized by the processor. the lpm block performs no tasks during this mode as long as the lpmcr(lpm) bits are set to 0,0. halt mode: only the xrs and xnmi external signals can wake the device from halt mode. the xnmi input to the core has an enable/disable bit. hence, it is safe to use the xnmi signal for this function. standby mode: all other signals (including xnmi) will wake the device from standby mode if selected by the lpmcr1 register. the user will need to select which signal(s) will wake the device. the selected signal(s) are also qualified by the oscclk before waking the device. the number of oscclks is specified in the lpmcr0 register. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 55 post office box 1443 ? houston, texas 77251 ? 1443 low-power modes block (continued) the low-power modes are controlled by the lpmcr0 register (see table 41) and the lpmcr1 register (see table 42). table 41. lpmcr0 register bit definitions bit(s) name type reset ? description 1,0 lpm ? r/w 0,0 these bits set the low power mode for the device. 7:2 qualstdby r/w 1:1 select number of oscclk clock cycles to qualify the selected inputs when waking the lpm from standby mode: 000000 = 2 oscclks 000001 = 3 oscclks . 111111 = 65 oscclks 15:8 reserved r=0 0:0 ? these bits are cleared by a reset (xrs ). ? the low power mode bits (lpm) are only valid when the idle instruction is executed. therefore, the user must set the lpm bits t o the appropriate mode before executing the idle instruction. table 42. lpmcr1 register bit definitions bit(s) name type reset ? description 0 xint1 r/w 0 1 xnmi r/w 0 2 wdint r/w 0 3 t1ctrip r/w 0 4 t2ctrip r/w 0 5 t3ctrip r/w 0 6 t4ctrip r/w 0 7 c1trip r/w 0 if the respective bit is set to 1, it will enable the selected si g nal to wake the 8 c2trip r/w 0 if the res ective bit is set to 1 , it will enable the selected signal to wake the device from standby mode. if the bit is cleared, the signal will have no effect. 9 c3trip r/w 0 10 c4trip r/w 0 11 c5trip r/w 0 12 c6trip r/w 0 13 scirxa r/w 0 14 scirxb r/w 0 15 canrx r/w 0 ? these bits are cleared by a reset (xrs ). pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 56 post office box 1443 ? houston, texas 77251 ? 1443 peripherals the integrated peripherals of the tms320f2810 and tms320f2812 are described in the following subsections: three 32-bit cpu-timers two event-manager modules (eva, evb) enhanced analog-to-digital converter (adc) module controller area network (can) module serial communications interface modules (sci-a, sci-b) serial peripheral interface (spi) module pll-based clock module digital i/o and shared pin functions external memory interfaces (tms320f2812 only) watchdog (wd) timer module 32-bit cpu-timers 0/1/2 this section describes the three 32-bit cpu-timers on the f2810 and f2812 devices (timer0/1/2). cpu-timers 1 and 2 are reserved for the real-time os (such as dsp-bios). ? cpu-timer 0 can be used in user applications. borrow reset timer reload sysclkout tcr.4 (timer start status) tint 16-bit timer divide-down tddrh:tddr 32-bit timer period prdh:prd 32-bit counter timh:tim 16-bit prescale counter psch:psc borrow note a: the cpu-timers are different from the general-purpose (gp) timers that are present in the event manager modules (eva, ev b). figure 12. cpu-timers pr o du c t preview ? if the application is not using bios, then cpu-timers 1 and 2 can be used in the application.
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 57 post office box 1443 ? houston, texas 77251 ? 1443 32-bit cpu-timers 0/1/2 (continued) in the f2810 and f2812 devices, the timer interrupt signals (tint0 , tint1 , tint2 ) are connected as shown in figure 13. int1 to int12 int14 c28x tint2 tint0 pie cpu-timer 0 cpu-timer 2 (for rtos use) int13 tint1 cpu-timer 1 (for rtos use) xint13 notes: a. the timer registers are connected to the memory bus of the c28x processor. b. the timing of the timers is synchronized to sysclkout of the processor clock. figure 13. cpu-timer interrupts signals and output signal the general operation of the timer is as follows: the 32-bit counter register ? timh:tim ? is loaded with the value in the period register ? prdh:prd ? . the counter register, decrements at the sysclkout rate of the c28x. when the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. the registers listed in table 43 are used to configure the timers. table 43. cpu-timers 0, 1, 2 configuration and control registers name address size (x16) description timer0tim 0x0000 ? 0c00 1 cpu-timer 0, counter register timer0timh 0x0000 ? 0c01 1 cpu-timer 0, counter register high timer0prd 0x0000 ? 0c02 1 cpu-timer 0, period register timer0prdh 0x0000 ? 0c03 1 cpu-timer 0, period register high timer0tcr 0x0000 ? 0c04 1 cpu-timer 0, control register reserved 0x0000 ? 0c05 1 timer0tpr 0x0000 ? 0c06 1 cpu-timer 0, prescale register timer0tprh 0x0000 ? 0c07 1 cpu-timer 0, prescale register high timer1tim 0x0000 ? 0c08 1 cpu-timer 1, counter register timer1timh 0x0000 ? 0c09 1 cpu-timer 1, counter register high timer1prd 0x0000 ? 0c0a 1 cpu-timer 1, period register timer1prdh 0x0000 ? 0c0b 1 cpu-timer 1, period register high timer1tcr 0x0000 ? 0c0c 1 cpu-timer 1, control register reserved 0x0000 ? 0c0d 1 timer1tpr 0x0000 ? 0c0e 1 cpu-timer 1, prescale register timer1tprh 0x0000 ? 0c0f 1 cpu-timer 1, prescale register high pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 58 post office box 1443 ? houston, texas 77251 ? 1443 32-bit cpu-timers 0/1/2 (continued) table 43. cpu-timers 0, 1, 2 configuration and control registers (continued) name address size (x16) description timer2tim 0x0000 ? 0c10 1 cpu-timer 2, counter register timer2timh 0x0000 ? 0c11 1 cpu-timer 2, counter register high timer2prd 0x0000 ? 0c12 1 cpu-timer 2, period register timer2prdh 0x0000 ? 0c13 1 cpu-timer 2, period register high timer2tcr 0x0000 ? 0c14 1 cpu-timer 2, control register reserved 0x0000 ? 0c15 1 timer2tpr 0x0000 ? 0c16 1 cpu-timer 2, prescale register timer2tprh 0x0000 ? 0c17 1 cpu-timer 2, prescale register high reserved 0x0000 ? 0c18 0x0000 ? 0c3f 40 table 44. timerxtim register bit definitions ? bits name r/w reset description 15:0 tim r/w 0xffff timer counter registers (timh:tim): the tim register holds the low 16 bits of the current 32-bit count of the timer. the timh register holds the high 16 bits of the current 32-bit count of the timer. the timh:tim decrements by one every (tddrh:tddr+1) clock cycles, where tddrh:tddr is the timer prescale divide-down value. when the timh:tim decrements to zero, the timh:tim register is reloaded with the period value contained in the prdh:prd registers. the timer interrupt (tint ) signal is generated. ? x = 0, 1, or 2 table 45. timerxtimh register bit definitions ? bits name r/w reset description 15:0 timh r/w 0x0000 see description for timerxtim. ? x = 0, 1, or 2 table 46. timerxprd register bit definitions ? bits name r/w reset description 15:0 prd r/w 0xffff timer period registers (prdh:prd): the prd register holds the low 16 bits of the 32-bit period. the prdh register holds the high 16 bits of the 32-bit period. when the timh:tim decrements to zero, the timh:tim register is reloaded with the period value contained in the prdh:prd registers, at the start of the next timer input clock cycle (the output of the prescaler). the prdh:prd contents are also loaded into the timh:tim when you set the timer reload bit (trb) in the timer control register (tcr). ? x = 0, 1, or 2 table 47. timerxprdh register bit definitions ? bits name r/w reset description 15:0 prdh r/w 0x0000 see description for timerxprd ? x = 0, 1, or 2 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 59 post office box 1443 ? houston, texas 77251 ? 1443 32-bit cpu-timers 0/1/2 (continued) table 48. timerxtcr register bit definitions ? bit name r/w reset description 15 tif r/w=1 0 timer interrupt flag. this flag gets set when the timer decrements to zero. this bit can be cleared by software writing a 1, but it can only be set by the timer reaching zero. writing a 1 to this bit will clear it, writing a zero has no effect. 14 tie r/w 0 timer interrupt enable. if the timer decrements to zero, and this bit is set, the timer will assert its interrupt request. 13:12 reserved r 0 reserved 11 free r/w 0 timer emulation modes: these bits are special emulation bits that determine the state of the timer when a breakpoint is encountered in the high-level language debugger. if the free bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is, free runs). in this case, soft is a don?t care . but if free is 0, then soft takes effect. in this case, if soft = 0, the timer halts the next time the timh:tim decrements. if the soft bit is 1, then the timer halts when the timh:tim has decremented to zero. free soft timer emulation mode 10 soft r/w 0 free soft timer emulation mode 0 0 stop after the next decrement of the timh:tim (hard stop) 0 1 stop after the timh:tim decrements to 0 (soft stop) 1 0 free run 1 1 free run note: that in the soft stop mode, the timer will generate an interrupt before shutting down (since reaching 0 is the interrupt causing condition). 9:6 reserved r/w 0 reserved 5 trb w/r=0 0 timer reload bit. when you write a 1 to trb, the timh:tim is loaded with the value in the prdh:prd, and the prescaler counter (psch:psc) is loaded with the value in the timer divide-down register (tddrh:tddr). the trb bit is always read as zero. 4 tss r/w 0 timer stop status bit. tss is a 1-bit flag that stops or starts the timer. to stop the timer, set tss to 1. to start or restart the timer, set tss to 0. at reset, tss is cleared to 0 and the timer immediately starts. 3:0 reserved r/w 0 reserved ? x = 0, 1, or 2 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 60 post office box 1443 ? houston, texas 77251 ? 1443 32-bit cpu-timers 0/1/2 (continued) table 49. timerxtpr register bit definitions ? bits name r/w reset description 7:0 tddr r/w 0x00 timer divide-down. every (tddrh:tddr + 1) timer clock source cycles, the timer counter register (timh:tim) decrements by one. at reset, the tddrh:tddr bits are cleared to 0. to increase the overall timer count by an integer factor, write this factor minus one to the tddrh:tddr bits. when the prescaler counter (psch:psc) value is 0, one timer clock source cycle later, the contents of the tddrh:tddr reload the psch:psc, and the timh:tim decrements by one. tddrh:tddr also reloads the psch:psc whenever the timer reload bit (trb) is set by software. 15:8 psc r 0x00 timer prescale counter. these bits hold the current prescale count for the timer. for every timer clock source cycle that the psch:psc value is greater than 0, the psch:psc decrements by one. one timer clock (output of the timer prescaler) cycle after the psch:psc reaches 0, the psch:psc is loaded with the contents of the tddrh:tddr, and the timer counter register (timh:tim) decrements by one. the psch:psc is also reloaded whenever the timer reload bit (trb) is set by software. the psch:psc can be checked by reading the register, but it cannot be set directly. it must get its value from the timer divide-down register (tddrh:tddr). at reset, the psch:psc is set to 0. ? x = 0, 1, or 2 table 50. timerxtprh register bit definitions ? bit name r/w reset description 7:0 tddrh r/w 0x00 see description of timerxtpr. 15:8 psch r 0x00 see description of timerxtpr. ? x = 0, 1, or 2 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 61 post office box 1443 ? houston, texas 77251 ? 1443 event manager modules (eva, evb) the event-manager modules include general-purpose (gp) timers, full-compare/pwm units, capture units, and quadrature-encoder pulse (qep) circuits. eva ? s and evb ? s timers, compare units, and capture units function identically. however, timer/unit names differ for eva and evb. table 51 shows the module and signal names used. table 51 shows the features and functionality available for the event-manager modules and highlights eva nomenclature. event managers a and b have identical peripheral register sets with eva starting at 7400h and evb starting at 7500h. the paragraphs in this section describe the function of gp timers, compare units, capture units, and qeps using eva nomenclature. these paragraphs are applicable to evb with regard to function ? however, module/signal names would differ. table 51. module and signal names for eva and evb event manager modules eva evb event manager modules module signal module signal gp timers gp timer 1 gp timer 2 t1pwm/t1cmp t2pwm/t2cmp gp timer 3 gp timer 4 t3pwm/t3cmp t4pwm/t4cmp compare units compare 1 compare 2 compare 3 pwm1/2 pwm3/4 pwm5/6 compare 4 compare 5 compare 6 pwm7/8 pwm9/10 pwm11/12 capture units capture 1 capture 2 capture 3 cap1 cap2 cap3 capture 4 capture 5 capture 6 cap4 cap5 cap6 qep channels qep1 qep2 qepi1 qep1 qep2 qep3 qep4 qepi2 qep3 qep4 external clock inputs direction external clock tdira tclkina direction external clock tdirb tclkinb external compare inputs compare c1trip c2trip c3trip c4trip c5trip c6trip external trip inputs t1ctrip_pdpinta ? t2ctrip /evasoc t3ctrip_pdpintb ? t4ctrip /evbsoc ? in the 24x/240x-compatible mode, the t1ctrip_pdpinta pin functions as pdpinta and the t3ctrip_pdpintb pin functions as pdpintb . pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 62 post office box 1443 ? houston, texas 77251 ? 1443 event manager modules (eva, evb) (continued) table 52. ev-a registers ? name address range size (x16) description gptcona 0x0000 ? 7400 1 gp timer control register a t1cnt 0x0000 ? 7401 1 gp timer 1 counter register t1cmpr 0x0000 ? 7402 1 gp timer 1 compare register t1pr 0x0000 ? 7403 1 gp timer 1 period register t1con 0x0000 ? 7404 1 gp timer 1 control register t2cnt 0x0000 ? 7405 1 gp timer 2 counter register t2cmpr 0x0000 ? 7406 1 gp timer 2 compare register t2pr 0x0000 ? 7407 1 gp timer 2 period register t2con 0x0000 ? 7408 1 gp timer 2 control register extcona ? 0x0000 ? 7409 1 gp extension control register a comcona 0x0000 ? 7411 1 compare control register a actra 0x0000 ? 7413 1 compare action control register a dbtcona 0x0000 ? 7415 1 dead-band timer control register a cmpr1 0x0000 ? 7417 1 compare register 1 cmpr2 0x0000 ? 7418 1 compare register 2 cmpr3 0x0000 ? 7419 1 compare register 3 capcona 0x0000 ? 7420 1 capture control register a capfifoa 0x0000 ? 7422 1 capture fifo status register a cap1fifo 0x0000 ? 7423 1 two-level deep capture fifo stack 1 cap2fifo 0x0000 ? 7424 1 two-level deep capture fifo stack 2 cap3fifo 0x0000 ? 7425 1 two-level deep capture fifo stack 3 cap1fbot 0x0000 ? 7427 1 bottom register of capture fifo stack 1 cap2fbot 0x0000 ? 7428 1 bottom register of capture fifo stack 2 cap2fbot 0x0000 ? 7429 1 bottom register of capture fifo stack 3 evaimra 0x0000 ? 742c 1 interrupt mask register a evaimrb 0x0000 ? 742d 1 interrupt mask register b evaimrc 0x0000 ? 742e 1 interrupt mask register c evaifra 0x0000 ? 742f 1 interrupt flag register a evaifrb 0x0000 ? 7430 1 interrupt flag register b evaifrc 0x0000 ? 7431 1 interrupt flag register c ? the ev-b register set is identical except the address range is from 0x0000 ? 7500 to 0x0000 ? 753f. the above registers are mapped to zone 2. this space allows only 16-bit accesses. 32-bit accesses produce undefined results. ? new register compared to 24x/240x pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 63 post office box 1443 ? houston, texas 77251 ? 1443 event manager modules (eva, evb) (continued) extcona is an added control register to enable and disable the added/modified features. it is required for compatibility with 24x ev. extcona enables and disables the additions and modifications in features. all additions and modifications are disabled by default to keep compatibility with 24x ev (see table 53). table 53. extcona register bit definitions bit(s) name type reset description 0 indcoe r/w 0 independent compare output enable mode: this bit, when set to one, allows compare outputs to be enabled and disabled independently. 0 1 independent compare output enable mode is disabled. time 1 and 2 compare outputs are enabled and disabled at the same time by gptcona(6). full compare 1, 2, and 3 outputs are enabled and disabled at the same time by comcona(9). gptcona(12,11,5,4) and comcona(7:5, 2:0) are reserved. evifra(0) enables and disables all the compare outputs at the same time. evimr(0) enables and disables pdp interrupt and the direct path of pdpint signal at the same time. independent compare output enable mode is enabled. compare outputs are enabled and disabled respectively by gptcona(5,4) and comcona(7:5). compare trips are enabled and disabled respectively by gptcona(12,11) and comcona(2:0). gptcona(6) and comcona(9) are reserved. evifra[0] is set to one when any trip input is low and is also enabled. evimra(0) functions only as interrupt enable and disable. 1 qepiqual r/w 0 qep/cap3 index qualification mode: this bit turns on and off qep index qualifier. 0 1 qepi/cap3 qualification mode is off. qepi/cap3 is allowed to pass the qualifier unaffected. qepi/cap3 qualification mode is on. a zero-to-one transition is allowed to pass the qualifier only when both qepa and qepb are high. otherwise the output of the qualifier stays low. 2 qepie r/w 0 qep index enable: this bit enables and disables the qepi input. the qepi input when enabled can cause timer 2 to reset: 0 1 disable qepi. transitions on qepi don ? t affect timer 2. enable qepi. either a zero-to-one transition on qepi alone (when extcona[1] = 0), or a zero-to-one transition plus qepa and qepb are both high (when extcona[1] = 1), causes timer 2 to reset to zero. 3 evsoce r/w 0 ev start-of-conversion output enable. this bit enables and disables the ev adc start-of-conversion output. when enabled, a negative (active-low) pulse of 32 x hspclk is generated on selected ev adc start-of-conversion event. this bit does not affect the evtoadc signal routed to the adc module as optional soc trigger. 0 1 disable evsoc output. evsoc is in hi-z state. enable evsoc output. 15:4 reserved r = 0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 64 post office box 1443 ? houston, texas 77251 ? 1443 event manager modules (eva, evb) (continued) gptcona(12:4), capcona(8), extcona[0] evtoadca timer 1 compare output logic t1pwm_t1cmp gptcona(1,0) t1con(1) gp timer 1 tclkina prescaler hspclk t1con(10:8) t1con(5,4) clock full compare 1 full compare 2 full compare 3 svpwm state machine dead- band logic output logic pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 t1con(15:11,6,3,2) tdira dir timer 2 compare gp timer 2 16 capture units comcona(15:5,2:0) pdpinta /t1ctrip , t2ctrip /evasoc, c1trip , c2trip , c3trip output logic t2pwm_t2cmp gptcona(3,2) t2con(1) t2con(15:11,7,6,3,2,0) actra(15:12), comcona(12), t1con(13:11) capcona(10,9) 16 dbtcona(15:0) actra(11:0) tclkina prescaler hspclk t2con(10:8) t2con(5,4) clock dir capcona(15:12,7:0) cap1_qep1 cap2_qep2 cap3_qepi1 qep logic qepclk qepdir 16 16 reset evaenclk control logic peripheral bus tdira index qual qepclk qepdir extcona(1:2) note a: the evb module is similar to the eva module. 16 figure 14. event manager a functional block diagram pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 65 post office box 1443 ? houston, texas 77251 ? 1443 general-purpose (gp) timers there are two gp timers. the gp timer x (x = 1 or 2 for eva; x = 3 or 4 for evb) includes: a 16-bit timer, up-/down-counter, txcnt, for reads or writes a 16-bit timer-compare register, txcmpr (double-buffered with shadow register), for reads or writes a 16-bit timer-period register, txpr (double-buffered with shadow register), for reads or writes a 16-bit timer-control register,txcon, for reads or writes selectable internal or external input clocks a programmable prescaler for internal or external clock inputs control and interrupt logic, for four maskable interrupts: underflow , overflow , timer compare , and period interrupts a selectable direction input pin (tdirx) (to count up or down when directional up- / down-count mode is selected) the gp timers can be operated independently or synchronized with each other. the compare register associated with each gp timer can be used for compare function and pwm-waveform generation. there are three continuous modes of operations for each gp timer in up- or up / down-counting operations. internal or external input clocks with programmable prescaler are used for each gp timer. gp timers also provide the time base for the other event-manager submodules: gp timer 1 for all the compares and pwm circuits, gp timer 2/1 for the capture units and the quadrature-pulse counting operations. double-buffering of the period and compare registers allows programmable change of the timer (pwm) period and the compare/pwm pulse width as needed. full-compare units there are three full-compare units on each event manager. these compare units use gp timer1 as the time base and generate six outputs for compare and pwm-waveform generation using programmable deadband circuit. the state of each of the six outputs is configured independently. the compare registers of the compare units are double-buffered, allowing programmable change of the compare/pwm pulse widths as needed. programmable deadband generator the deadband generator circuit includes three 8-bit counters and an 8-bit compare register. desired deadband values can be programmed into the compare register for the outputs of the three compare units. the deadband generation can be enabled/disabled for each compare unit output individually. the deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. the output states of the deadband generator are configurable and changeable as needed by way of the double-buffered actrx register. pwm waveform generation up to eight pwm waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands , and two independent pwms by the gp-timer compares. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 66 post office box 1443 ? houston, texas 77251 ? 1443 pwm characteristics characteristics of the pwms are as follows: 16-bit registers wide range of programmable deadband for the pwm output pairs change of the pwm carrier frequency for pwm frequency wobbling as needed change of the pwm pulse widths within and after each pwm period as needed external-maskable power and drive-protection interrupts pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector pwm waveforms minimized cpu overhead using auto-reload of the compare and period registers the pwm pins are driven to a high-impedance state when the pdpintx pin is driven low and after pdpintx signal qualification. the pdpintx pin (after qualification) is reflected in bit 8 of the comconx register. ? pdpinta pin status is reflected in bit 8 of comcona register. ? pdpintb pin status is reflected in bit 8 of comconb register. capture unit the capture unit provides a logging function for different events or transitions. the values of the selected gp timer counter is captured and stored in the two-level-deep fifo stacks when selected transitions are detected on capture input pins, capx (x = 1, 2, or 3 for eva; and x = 4, 5, or 6 for evb). the capture unit consists of three capture circuits. capture units include the following features: ? one 16-bit capture control register, capconx (r/w) ? one 16-bit capture fifo status register, capfifox ? selection of gp timer 1/2 (for eva) or 3/4 (for evb) as the time base ? three 16-bit 2-level-deep fifo stacks, one for each capture unit ? three capture input pins (cap1/2/3 for eva, cap4/5/6 for evb) ? one input pin per capture unit. [all inputs are synchronized with the device (cpu) clock. in order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. the input pins cap1/2 and cap4/5 can also be used as qep inputs to the qep circuit.] ? user-specified transition (rising edge, falling edge, or both edges) detection ? three maskable interrupt flags, one for each capture unit quadrature-encoder pulse (qep) circuit two capture inputs (cap1 and cap2 for eva; cap4 and cap5 for evb) can be used to interface the on-chip qep circuit with a quadrature encoder pulse. full synchronization of these inputs is performed on-chip. direction or leading-quadrature pulse sequence is detected, and gp timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). external adc start-of-conversion eva/evb start-of-conversion (soc) can be sent to an external pin (esoca/b) for external adc interface. evasoc and evbsoc are muxed with t2ctrip and t4ctrip , respectively. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 67 post office box 1443 ? houston, texas 77251 ? 1443 enhanced analog-to-digital converter (adc) module a simplified functional block diagram of the adc module is shown in figure 15. the adc module consists of a 12-bit adc with a built-in sample-and-hold (s / h) circuit. functions of the adc module include: 12-bit adc core with built-in s/h analog input: 0 v to 2.5 v fast conversion time: ? single conversion time: 200 ns ? pipelined conversion time: 60 ns 16-channel, muxed inputs autosequencing capability provides up to 16 ? autoconversions ? in a single session. each conversion can be programmed to select any 1 of 16 input channels sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) sixteen result registers (individually addressable) to store conversion values ? the digital value of the input analog voltage is derived by: digital value 4095 input analog voltage adclo 2.5 multiple triggers as sources for the start-of-conversion (soc) sequence ? s/w ? software immediate start ? eva ? event manager a (multiple event sources within eva) ? evb ? event manager b (multiple event sources within evb) flexible interrupt control allows interrupt request on every end-of-sequence (eos) or every other eos sequencer can operate in ? start/stop ? mode, allowing multiple ? time-sequenced triggers ? to synchronize conversions eva and evb triggers can operate independently in dual-sequencer mode sample-and-hold (s/h) acquisition time window has separate prescale control calibration mode pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 68 post office box 1443 ? houston, texas 77251 ? 1443 enhanced analog-to-digital converter (adc) module (continued) the adc module in the f2810 and f2812 has been enhanced to provide flexible interface to event managers a and b. the adc interface is built around a fast, 12-bit adc module with a total minimum conversion time of 200 ns (s/h + conversion) per conversion. the adc module has 16 channels, configurable as two independent 8-channel modules to service event managers a and b. the two independent 8-channel modules can be cascaded to form a 16-channel module. although there are multiple input channels and two sequencers, there is only one converter in the adc module. figure 15 shows the block diagram of the f2810 and f2812 adc module. the two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog mux. in the cascaded mode, the autosequencer functions as a single 16-channel sequencer. on each sequencer, once the conversion is complete, the selected channel value is stored in its respective result register. autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. this gives increased resolution over traditional single-sampled conversion results. result registers evb s/w adcsoc eva s/w sequencer 2 sequencer 1 soc soc adc control registers 70b7h 70b0h 70afh 70a8h result reg 15 result reg 8 result reg 7 result reg 1 result reg 0 module adc 12-bit analog mux adcin00 adcin07 adcin08 adcin15 low-power modes block system control block high-speed prescaler halt hspclk adcenclk c28x sysclkout s/h s/h figure 15. block diagram of the f2810 and f2812 adc module pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 69 post office box 1443 ? houston, texas 77251 ? 1443 enhanced analog-to-digital converter (adc) module (continued) to obtain the specified accuracy of the adc, proper board layout is very critical. to the best extent possible, traces leading to the adcin pins should not run in close proximity to the digital signal paths. this is to minimize switching noise on the digital lines from getting coupled to the adc inputs. furthermore, proper isolation techniques must be used to isolate the adc module power pins (such as v cca , v refhi , and v ssa ) from the digital supply. notes: 1. the adc registers are accessed at the sysclkout rate. the internal timing of the adc module is controlled by the high-speed peripheral clock (hspclk). 2. the behavior of the adc module based on the state of the adcenclk and halt signals is as follows: adcenclk: on reset, this signal will be low. while reset is active-low (xrs ) the clock to the register will still function. this is necessary to make sure all registers and modes go into their default reset state. the analog module will however be in a low-power inactive state. as soon as reset goes high, then the clock to the registers will be disabled. when the user sets the adcenclk signal high, then the clocks to the registers will be enabled and the analog module will be enabled. there will be a certain time delay (ms range) before the adc is stable and can be used. halt: this signal only affects the analog module. it does not affect the registers. if low, the adc module is powered. if high, the adc module goes into low-power mode. the halt mode will stop the clock to the cpu, which will stop the hspclk. therefore the adc register logic will be turned off indirectly. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 70 post office box 1443 ? houston, texas 77251 ? 1443 enhanced analog-to-digital converter (adc) module (continued) the adc operation is configured, controlled, and monitored by the registers listed in table 54. table 54. adc registers ? name address range size (x16) description adctrl1 0x0000 ? 7100 1 adc control register 1 adctrl2 0x0000 ? 7101 1 adc control register 2 adcmaxconv 0x0000 ? 7102 1 adc maximum conversion channels register adcchselseq1 0x0000 ? 7103 1 adc channel select sequencing control register 1 adcchselseq2 0x0000 ? 7104 1 adc channel select sequencing control register 2 adcchselseq3 0x0000 ? 7105 1 adc channel select sequencing control register 3 adcchselseq4 0x0000 ? 7106 1 adc channel select sequencing control register 4 adcaseqsr 0x0000 ? 7107 1 adc auto ? sequence status register adcresult0 0x0000 ? 7108 1 adc conversion result buffer register 0 adcresult1 0x0000 ? 7109 1 adc conversion result buffer register 1 adcresult2 0x0000 ? 710a 1 adc conversion result buffer register 2 adcresult3 0x0000 ? 710b 1 adc conversion result buffer register 3 adcresult4 0x0000 ? 710c 1 adc conversion result buffer register 4 adcresult5 0x0000 ? 710d 1 adc conversion result buffer register 5 adcresult6 0x0000 ? 710e 1 adc conversion result buffer register 6 adcresult7 0x0000 ? 710f 1 adc conversion result buffer register 7 adcresult8 0x0000 ? 7110 1 adc conversion result buffer register 8 adcresult9 0x0000 ? 7111 1 adc conversion result buffer register 9 adcresult10 0x0000 ? 7112 1 adc conversion result buffer register 10 adcresult11 0x0000 ? 7113 1 adc conversion result buffer register 11 adcresult12 0x0000 ? 7114 1 adc conversion result buffer register 12 adcresult13 0x0000 ? 7115 1 adc conversion result buffer register 13 adcresult14 0x0000 ? 7116 1 adc conversion result buffer register 14 adcresult15 0x0000 ? 7117 1 adc conversion result buffer register 15 adccaloff0 0x0000 ? 7118 1 adc calibration offset result 0 adccaloff1 0x0000 ? 7119 1 adc calibration offset result 1 adctrl3 0x0000 ? 711a 1 adc control register 3 adcst 0x0000 ? 711b 1 adc status register reserved 0x0000 ? 711c 0x0000 ? 711f 4 ? the above registers are mapped to peripheral bus 16 space. this space only allows 16-bit accesses. 32-bit accesses produce unde fined results. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 71 post office box 1443 ? houston, texas 77251 ? 1443 enhanced controller area network (ecan) module the can module has the following features: fully compliant with can protocol, version 2.0b supports data rates up to 1 mbps thirty-two mailboxes, each with the following properties: ? configurable as receive or transmit ? configurable with standard or extended identifier ? has a programmable receive mask ? supports data and remote frame ? composed of 0 to 8 bytes of data ? uses a 32-bit time stamp on receive and transmit message ? protects against reception of new message ? holds the dynamically programmable priority of transmit message ? employs a programmable interrupt scheme with two interrupt levels ? employs a programmable alarm on transmission or reception time-out low-power mode programmable wake-up on bus activity automatic reply to a remote request message automatic retransmission of a frame in case of loss of arbitration or error 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) self-test mode ? operates in a loopback mode receiving its own message. a ? dummy ? acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 72 post office box 1443 ? houston, texas 77251 ? 1443 enhanced controller area network (ecan) module (continued) mailbox ram (512 bytes) 32-message mailbox of 4 32-bit words memory management unit cpu interface, receive control unit, timer management unit ecan memory (512 bytes) registers and message objects control 32 32 message controller 32 32 32 32 32 32 ecan protocol kernel receive buffer transmit buffer control buffer status buffer enhanced can controller 32 controls address data hecc1int hecc0int 32 sn65hvd23x 3.3-v can transceiver can bus figure 16. ecan block diagram and interface circuit pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 73 post office box 1443 ? houston, texas 77251 ? 1443 enhanced controller area network (ecan) module (continued) mailbox enable ? canme mailbox direction ? canmd transmission request set ? cantrs transmission request reset ? cantrr transmission acknowledge ? canta abort acknowledge ? canaa receive message pending ? canrmp receive message lost ? canrml remote frame pending ? canrfp reserved master control ? canmc bit-timing configuration ? canbtc error and status ? canes transmit error counter ? cantec receive error counter ? canrec global interrupt flag 0 ? cangif0 global interrupt mask ? cangim mailbox interrupt mask ? canmim mailbox interrupt level ? canmil overwrite protection control ? canopc tx i/o control ? cantioc rx i/o control ? canrioc local network time ? canlnt global interrupt flag 1 ? cangif1 time-out control ? cantoc time-out status ? cantos reserved ecan control and status registers message identifier ? mid 61e8h ? 61e9h message control ? mcf message data low ? mdl message data high ? mdh message mailbox (16 bytes) control and status registers 6000h 603fh local acceptance masks (lam) (32 32-bit ram) 6040h 607fh 6080h 60bfh 60c0h 60ffh ecan memory (512 bytes) message object time stamps (mots) (32 32-bit ram) message object time-out (moto) (32 32-bit ram) mailbox 0 6100h ? 6107h mailbox 1 6108h ? 610fh mailbox 2 6110h ? 6117h mailbox 3 6118h ? 611fh ecan memory ram (512 bytes) mailbox 4 6120h ? 6127h mailbox 28 61e0h ? 61e7h mailbox 29 61e8h ? 61efh mailbox 30 61f0h ? 61f7h mailbox 31 61f8h ? 61ffh 61eah ? 61ebh 61ech ? 61edh 61eeh ? 61efh figure 17. ecan memory map pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 74 post office box 1443 ? houston, texas 77251 ? 1443 enhanced controller area network (ecan) module (continued) the can registers listed in table 55 are used by the cpu to configure and control the can controller and the message objects. table 55. can registers map ? register name address description canme 0x00 6000 mailbox enable canmd 0x00 6002 mailbox direction cantrs 0x00 6004 transmit request set cantrr 0x00 6006 transmit request reset canta 0x00 6008 transmission acknowledge canaa 0x00 600a abort acknowledge canrmp 0x00 600c receive message pending canrml 0x00 600e receive message lost canrfp 0x00 6010 remote frame pending reserved 0x00 6012 reserved canmc 0x00 6014 master control canbtc 0x00 6016 bit-timing configuration canes 0x00 6018 error and status cantec 0x00 601a transmit error counter canrec 0x00 601c receive error counter cangif0 0x00 601e global interrupt flag 0 cangim 0x00 6020 global interrupt mask cangif1 0x00 6022 global interrupt flag 1 canmim 0x00 6024 mailbox interrupt mask canmil 0x00 6026 mailbox interrupt level canopc 0x00 6028 overwrite protection control cantioc 0x00 602a tx i/o control canrioc 0x00 602c rx i/o control canlnt 0x00 602e local network time (reserved in scc mode) cantoc 0x00 6030 time-out control (reserved in scc mode) cantos 0x00 6032 time-out status (reserved in scc mode) ? these registers are mapped to peripheral frame 1. this space allows 16-bit and 32-bit accesses. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 75 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port (mcbsp) module the mcbsp module has the following features: compatible to mcbsp in tms320c54x ? /tms320c55x ? dsp devices full-duplex communication double-buffered data registers which allow a continuous data stream independent framing and clocking for receive and transmit external shift clock generation or an internal programmable frequency shift clock a wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits 8-bit data transfers with lsb or msb first programmable polarity for both frame synchronization and data clocks highly programmable internal clock and frame generation support a-bis mode direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected a/d and d/a devices works with spi-compatible devices at 75 mbps maximum for 150-mhz sysclkout two 16 x 16-level fifo for transmit channel two 16 x 16-level fifo for receive channel the following application interfaces can be supported on the mcbsp: t1/e1 framers mvip switching-compatible and st-bus-compliant devices including: ? mvip framers ? h.100 framers ? scsa framers ? iom-2 compliant devices ? ac97-compliant devices (the necessary multiphase frame synchronization capability is provided.) ? iis-compliant devices pr o du c t preview tms320c54x and tms320c55x are trademarks of texas instruments.
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 76 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port (mcbsp) module (continued) figure 18 shows the block diagram of the mcbsp module with fifo, interfaced to the f2810 and f2812 version of peripheral frame 2. mcbsp receive interrupt select logic dx dr expand logic drr1 receive buffer rx fifo interrupt drr2 receive buffer rx fifo registers rbr1 register rbr2 register mcbsp registers and control logic clkx fsx clkr fsr 16 compand logic dxr2 transmit buffer rsr1 xsr2 xsr1 peripheral read bus 16 16 16 16 16 rsr2 dxr1 transmit buffer 16 lspclk mrint to cpu mcbsp rx interrupt logic rx fifo _15 ? rx fifo _1 rx fifo _0 rx fifo _15 ? rx fifo _1 rx fifo _0 mcbsp transmit interrupt select logic tx fifo interrupt tx fifo registers mxint to cpu tx interrupt logic 16 16 16 tx fifo _15 ? tx fifo _1 tx fifo _0 tx fifo _15 ? tx fifo _1 tx fifo _0 peripheral write bus figure 18. mcbsp module with fifo pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 77 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port (mcbsp) module (continued) table 56 provides a summary of the mcbsp registers. table 56. mcbsp register summary name address 0x000 xxh type (r/w) reset value (hex) description data registers, receive, transmit ? ? ? ? 0x0000 mcbsp receive buffer register ? ? ? 0x0000 mcbsp receive shift register ? ? ? 0x0000 mcbsp transmit shift register drr2 00 r 0x0000 mcbsp data receive register 2 ? read first if the word size is greater than 16 bits, else ignore drr2 drr1 01 r 0x0000 mcbsp data receive register 1 ? read second if the word size is greater than 16 bits, else read drr1 only dxr2 02 w 0x0000 mcbsp data transmit register 2 ? write first if the word size is greater than 16 bits, else ignore dxr2 dxr1 03 w 0x0000 mcbsp data transmit register 1 ? write second if the word size is greater than 16 bits, else write to dxr1 only mcbsp control registers spcr2 04 r/w 0x0000 mcbsp serial port control register 2 spcr1 05 r/w 0x0000 mcbsp serial port control register 1 rcr2 06 r/w 0x0000 mcbsp receive control register 2 rcr1 07 r/w 0x0000 mcbsp receive control register 1 xcr2 08 r/w 0x0000 mcbsp transmit control register 2 xcr1 09 r/w 0x0000 mcbsp transmit control register 1 srgr2 0a r/w 0x0000 mcbsp sample rate generator register 2 srgr1 0b r/w 0x0000 mcbsp sample rate generator register 1 multichannel control registers mcr2 0c r/w 0x0000 mcbsp multichannel register 2 mcr1 0d r/w 0x0000 mcbsp multichannel register 1 rcera 0e r/w 0x0000 mcbsp receive channel enable register partition a rcerb 0f r/w 0x0000 mcbsp receive channel enable register partition b xcera 10 r/w 0x0000 mcbsp transmit channel enable register partition a xcerb 11 r/w 0x0000 mcbsp transmit channel enable register partition b pcr1 12 r/w 0x0000 mcbsp pin control register rcerc 13 r/w 0x0000 mcbsp receive channel enable register partition c rcerd 14 r/w 0x0000 mcbsp receive channel enable register partition d xcerc 15 r/w 0x0000 mcbsp transmit channel enable register partition c xcerd 16 r/w 0x0000 mcbsp transmit channel enable register partition d ? drr2/drr1 and dxr2/dxr1 share the same addresses of receive and transmit fifo registers in fifo mode. ? fifo pointers advancing is based on order of access to drr2/drr1 and dxr2/dxr1 registers. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 78 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port (mcbsp) module (continued) table 56. mcbsp register summary (continued) name address 0x000 xxh type (r/w) reset value (hex) description multichannel control registers (continued) rcere 17 r/w 0x0000 mcbsp receive channel enable register partition e rcerf 18 r/w 0x0000 mcbsp receive channel enable register partition f xcere 19 r/w 0x0000 mcbsp transmit channel enable register partition e xcerf 1a r/w 0x0000 mcbsp transmit channel enable register partition f rcerg 1b r/w 0x0000 mcbsp receive channel enable register partition g rcerh 1c r/w 0x0000 mcbsp receive channel enable register partition h xcerg 1d r/w 0x0000 mcbsp transmit channel enable register partition g xcerh 1e r/w 0x0000 mcbsp transmit channel enable register partition h fifo mode registers (applicable only in fifo mode) fifo data registers ? drr2 00 r 0x0000 mcbsp data receive register 2 ? top of receive fifo ? read first fifo pointers will not advance drr1 01 r 0x0000 mcbsp data receive register 1 ? top of receive fifo ? read second for fifo pointers to advance dxr2 02 w 0x0000 mcbsp data transmit register 2 ? top of transmit fifo ? write first fifo pointers will not advance dxr1 03 w 0x0000 mcbsp data transmit register 1 ? top of transmit fifo ? write second for fifo pointers to advance fifo control registers mfftx 20 r/w 0xa000 mcbsp transmit fifo register mffrx 21 r/w 0x201f mcbsp receive fifo register mffct 22 r/w 0x0000 mcbsp fifo control register mffint 23 r/w 0x0000 mcbsp fifo interrupt register mffst 24 r/w 0x0000 mcbsp fifo status register ? drr2/drr1 and dxr2/dxr1 share the same addresses of receive and transmit fifo registers in fifo mode. ? fifo pointers advancing is based on order of access to drr2/drr1 and dxr2/dxr1 registers. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 79 post office box 1443 ? houston, texas 77251 ? 1443 serial communications interface (sci) module the f2810 and f2812 devices include two serial communications interface (sci) modules. the sci modules support digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the sci receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. to ensure data integrity, the sci checks received data for break detection, parity, overrun, and framing errors. the bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. features of the sci module include: two external pins: ? scitxd: sci transmit-output pin ? scirxd: sci receive-input pin note: both pins can be used as gpio if not used for sci. baud rate programmable to 64k different rates ? up to 9.3 mbps at 150-mhz sysclkout data-word format ? one start bit ? data-word length programmable from one to eight bits ? optional even/odd/no parity bit ? one or two stop bits four error-detection flags: parity, overrun, framing, and break detection two wake-up multiprocessor modes: idle-line and address bit half- or full-duplex operation double-buffered receive and transmit functions transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. ? transmitter: txrdy flag (transmitter-buffer register is ready to receive another character) and tx empty flag (transmitter-shift register is empty) ? receiver: rxrdy flag (receiver-buffer register is ready to receive another character), brkdt flag (break condition occurred), and rx error flag (monitoring four interrupt conditions) separate enable bits for transmitter and receiver interrupts (except brkdt) nrz (non-return-to-zero) format ten sci module control registers located in the control register frame beginning at address 7050h note: all registers in this module are 8-bit registers that are connected to peripheral frame 2. when a register is accessed, th e register data is in the lower byte (7 ? 0), and the upper byte (15 ? 8) is read as zeros. writing to the upper byte has no effect. enhanced features: auto baud-detect hardware logic 16-level transmit/receive fifo pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 80 post office box 1443 ? houston, texas 77251 ? 1443 serial communications interface (sci) module (continued) the sci port operation is configured and controlled by the registers listed in table 57 and table 58. table 57. sci-a registers ? name address range size (x16) description sciccr 0x0000 ? 7050 1 sci-a communications control register scictl1 0x0000 ? 7051 1 sci-a control register 1 scihbaud 0x0000 ? 7052 1 sci-a baud register, high bits scilbaud 0x0000 ? 7053 1 sci-a baud register, low bits scictl2 0x0000 ? 7054 1 sci-a control register 2 scirxst 0x0000 ? 7055 1 sci-a receive status register scirxemu 0x0000 ? 7056 1 sci-a receive emulation data buffer register scirxbuf 0x0000 ? 7057 1 sci-a receive data buffer register scitxbuf 0x0000 ? 7059 1 sci-a transmit data buffer register scifftx 0x0000 ? 705a 1 sci-a fifo transmit register sciffrx 0x0000 ? 705b 1 sci-a fifo receive register sciffct 0x0000 ? 705c 1 sci-a fifo control register scipri 0x0000 ? 705f 1 sci-a priority control register ? shaded registers are new registers for the fifo mode. table 58. sci-b registers ? name address range size (x16) description sciccr 0x0000 ? 7750 1 sci-b communications control register scictl1 0x0000 ? 7751 1 sci-b control register 1 scihbaud 0x0000 ? 7752 1 sci-b baud register, high bits scilbaud 0x0000 ? 7753 1 sci-b baud register, low bits scictl2 0x0000 ? 7754 1 sci-b control register 2 scirxst 0x0000 ? 7755 1 sci-b receive status register scirxemu 0x0000 ? 7756 1 sci-b receive emulation data buffer register scirxbuf 0x0000 ? 7757 1 sci-b receive data buffer register scitxbuf 0x0000 ? 7759 1 sci-b transmit data buffer register scifftx 0x0000 ? 775a 1 sci-b fifo transmit register sciffrx 0x0000 ? 775b 1 sci-b fifo receive register sciffct 0x0000 ? 775c 1 sci-b fifo control register scipri 0x0000 ? 775f 1 sci-b priority control register ? shaded registers are new registers for the fifo mode. note: the above registers are mapped to peripheral bus 16 space. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 81 post office box 1443 ? houston, texas 77251 ? 1443 serial communications interface (sci) module (continued) figure 19 shows the sci module block diagram. tx fifo _0 lspclk wut frame format and mode even/odd enable parity sci rx interrupt select logic brkdt rxrdy scirxst.6 scictl1.3 8 scictl2.1 rx/bk int ena scirxd scirxst.1 txena sci tx interrupt select logic tx empty txrdy scictl2.0 tx int ena scitxd rxena scirxd rxwake scictl1.6 rx err int ena txwake scitxd sciccr.6 sciccr.5 scitxbuf.7?0 scihbaud. 15 ? 8 baud rate msbyte register scilbaud. 7 ? 0 transmitter ? data buffer register 8 scictl2.6 scictl2.7 baud rate lsbyte register rxshf register txshf register scirxst.5 1 tx fifo _1 ????? tx fifo _15 8 tx fifo registers tx fifo interrupt tx interrupt logic txint scifftx.14 rx fifo _15 scirxbuf.7?0 receive data buffer register scirxbuf.7 ? 0 ????? rx fifo_1 rx fifo _0 8 rx fifo registers scictl1.0 rx interrupt logic rxint rx fifo interrupt sciffrx.15 rxffovf rx error scirxst.7 pe fe oe rx error scirxst.4 ? 2 to cpu to cpu autobaud detect logic scictl1.1 sciffena figure 19. serial communications interface (sci) module block diagram pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 82 post office box 1443 ? houston, texas 77251 ? 1443 serial peripheral interface (spi) module the f2810 and f2812 devices include the four-pin serial peripheral interface (spi) module. the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multidevice communications are supported by the master/slave operation of the spi. the spi module features include: four external pins: ? spisomi: spi slave-output/master-input pin ? spisimo: spi slave-input/master-output pin ? spiste : spi slave transmit-enable pin ? spiclk: spi serial-clock pin note: all four pins can be used as gpio, if the spi module is not used. two operational modes: master and slave baud rate: 125 different programmable rates / 37.5 mbps at 150-mhz sysclkout data word length: one to sixteen data bits four clocking schemes (controlled by clock polarity and clock phase bits) include: ? falling edge without phase delay: spiclk active-high. spi transmits data on the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. ? falling edge with phase delay: spiclk active-high. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge without phase delay: spiclk inactive-low. spi transmits data on the rising edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge with phase delay: spiclk inactive-low. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. simultaneous receive and transmit operation (transmit function can be disabled in software) transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. nine spi module control registers: located in control register frame beginning at address 7040h. note: all registers in this module are 16-bit registers that are connected to peripheral frame 2. when a register is accessed, t he register data is in the lower byte (7 ? 0), and the upper byte (15 ? 8) is read as zeros. writing to the upper byte has no effect. enhanced feature: 16-level transmit/receive fifo delayed transmit control pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 83 post office box 1443 ? houston, texas 77251 ? 1443 serial peripheral interface (spi) module (continued) the spi port operation is configured and controlled by the registers listed in table 59. table 59. spi registers name address range size (x16) description spiccr 0x0000 ? 7040 1 spi configuration control register spictl 0x0000 ? 7041 1 spi operation control register spist 0x0000 ? 7042 1 spi status register spibrr 0x0000 ? 7044 1 spi baud rate register spiemu 0x0000 ? 7046 1 spi emulation buffer register spirxbuf 0x0000 ? 7047 1 spi serial input buffer register spitxbuf 0x0000 ? 7048 1 spi serial output buffer register spidat 0x0000 ? 7049 1 spi serial data register spifftx 0x0000 ? 704a 1 spi fifo transmit register spiffrx 0x0000 ? 704b 1 spi fifo receive register spiffct 0x0000 ? 704c 1 spi fifo control register spipri 0x0000 ? 704f 1 spi priority control register note: the above registers are mapped to peripheral frame 2. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 84 post office box 1443 ? houston, texas 77251 ? 1443 serial peripheral interface (spi) module (continued) figure 20 is a block diagram of the spi in slave mode. s spictl.0 spi int flag spi int ena spists.6 s clock polarity talk lspclk 4 5 61 2 30 0 1 2 3 spi bit rate state control spirxbuf buffer register clock phase receiver overrun flag spictl.4 overrun int ena spiccr.3 ? 0 spibrr.6 ? 0 spiccr.6 spictl.3 spidat.15 ? 0 spictl.1 m s m master/slave spists.7 spidat data register m s spictl.2 spi char spisimo spisomi spiste * spiclk sw2 s m m s sw3 to cpu m sw1 spitxbuf buffer register rx fifo _0 rx fifo _1 ????? rx fifo _15 tx fifo registers tx fifo _0 tx fifo _1 ????? tx fifo _15 rx fifo registers 16 16 16 tx interrupt logic rx interrupt logic spiint spitx spiffovf flag spiffrx.15 16 tx fifo interrupt rx fifo interrupt spirxbuf spitxbuf spifftx.14 spiffena figure 20. serial peripheral interface module block diagram pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 85 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux the gpio mux registers, are used to select the operation of shared pins on the f2810 and f2812 devices. the pins can be individually selected to operate as ? digital i/o ? or connected to ? peripheral i/o ? signals (via the gpxmux registers). if selected for ? digital i/o ? mode, registers are provided to configure the pin direction (via the gpxdir registers) and to qualify the input signal to remove unwanted noise (via the gpxqual) registers). table 60 lists the gpio mux registers. table 60. gpio mux registers ?? name address size (x16) register description gpamux 0x0000 ? 70c0 1 gpio a mux control register gpadir 0x0000 ? 70c1 1 gpio a direction control register gpaqual 0x0000 ? 70c2 1 gpio a input qualification control register reserved 0x0000 ? 70c3 1 gpbmux 0x0000 ? 70c4 1 gpio b mux control register gpbdir 0x0000 ? 70c5 1 gpio b direction control register gpbqual 0x0000 ? 70c6 1 gpio b input qualification control register reserved 0x0000 ? 70c7 1 reserved 0x0000 ? 70c8 1 reserved 0x0000 ? 70c9 1 reserved 0x0000 ? 70ca 1 reserved 0x0000 ? 70cb 1 gpdmux 0x0000 ? 70cc 1 gpio d mux control register gpddir 0x0000 ? 70cd 1 gpio d direction control register gpdqual 0x0000 ? 70ce 1 gpio d input qualification control register reserved 0x0000 ? 70cf 1 gpemux 0x0000 ? 70d0 1 gpio e mux control register gpedir 0x0000 ? 70d1 1 gpio e direction control register gpequal 0x0000 ? 70d2 1 gpio e input qualification control register reserved 0x0000 ? 70d3 1 gpfmux 0x0000 ? 70d4 1 gpio f mux control register gpfdir 0x0000 ? 70d5 1 gpio f direction control register reserved 0x0000 ? 70d6 1 reserved 0x0000 ? 70d7 1 gpgmux 0x0000 ? 70d8 1 gpio f mux control register gpgdir 0x0000 ? 70d9 1 gpio f direction control register reserved 0x0000 ? 70da 1 reserved 0x0000 ? 70db 1 reserved 0x0000 ? 70dc 0x0000 ? 70df 4 ? registers that are not implemented will return undefined values and writes will be ignored. ? not all inputs will support input signal qualification. these registers are eallow protected. this prevents spurious writes from overwriting the contents and corrupting the system. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 86 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) if configured for ? digital i/o ? mode, additional registers are provided for setting individual i/o signals (via the gpxset registers), for clearing individual i/o signals (via the gpxclear registers), for toggling individual i/o signals (via the gpxtoggle registers), or for reading/writing to the individual i/o signals (via the gpxdat registers). table 61 lists the gpio data registers. table 61. gpio data registers ?? name address size (x16) register description gpadat 0x0000 ? 70e0 1 gpio a data register gpaset 0x0000 ? 70e1 1 gpio a set register gpaclear 0x0000 ? 70e2 1 gpio a clear register gpatoggle 0x0000 ? 70e3 1 gpio a toggle register gpbdat 0x0000 ? 70e4 1 gpio b data register gpbset 0x0000 ? 70e5 1 gpio b set register gpbclear 0x0000 ? 70e6 1 gpio b clear register gpbtoggle 0x0000 ? 70e7 1 gpio b toggle register reserved 0x0000 ? 70e8 1 reserved 0x0000 ? 70e9 1 reserved 0x0000 ? 70ea 1 reserved 0x0000 ? 70eb 1 gpddat 0x0000 ? 70ec 1 gpio d data register gpdset 0x0000 ? 70ed 1 gpio d set register gpdclear 0x0000 ? 70ee 1 gpio d clear register gpdtoggle 0x0000 ? 70ef 1 gpio d toggle register gpedat 0x0000 ? 70f0 1 gpio e data register gpeset 0x0000 ? 70f1 1 gpio e set register gpeclear 0x0000 ? 70f2 1 gpio e clear register gpetoggle 0x0000 ? 70f3 1 gpio e toggle register gpfdat 0x0000 ? 70f4 1 gpio f data register gpfset 0x0000 ? 70f5 1 gpio f set register gpfclear 0x0000 ? 70f6 1 gpio f clear register gpftoggle 0x0000 ? 70f7 1 gpio f toggle register gpgdat 0x0000 ? 70f8 1 gpio g data register gpgset 0x0000 ? 70f9 1 gpio g set register gpgclear 0x0000 ? 70fa 1 gpio g clear register gpgtoggle 0x0000 ? 70fb 1 gpio g toggle register reserved 0x0000 ? 70fc 0x0000 ? 70ff 4 ? reserved locations will return undefined values and writes will be ignored. ? these registers are not eallow protected. the above registers will typically be accessed regularly by the user. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 87 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) figure 21 shows how the various register bits select the various modes of operation. peripheral i/o mux 01 mux 1 0 pin internal (pullup or pulldown) hspclk (high-speed peripheral clock) digital i/o qualxclk boundary off xrs high-impedance enable (1) high- impedance control gpxdir register bit gpxmux register bit gpxqual register gpxdat/set/clear/toggle register bit(s) input qualification pre-scale figure 21. modes of operation notes: 1. via the gpxdat register, the state of any pin can be read, regardless of the operating mode. 2. some selected input signals are, qualified by the qualxclk, which is a prescaled version of the high-speed peripheral clock (hspclk). the gpxqual register specifies the qualification sampling period. the sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0 ? s or all 1 ? s) as shown in figure 22. this feature removes unwanted spikes from the input signal. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 88 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) input to qual 1 sampling window qualprd output from qual 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 figure 22. i/p qualifier clock cycles table 62. gpamux, gpadir register bit definitions gpamux bit peripheral name (bit = 1) gpio name (bit = 0) gpadir bit type reset input qual ev-a peripheral 0 pwm1 (o) gpioa0 0 r/w 0 yes 1 pwm2 (o) gpioa1 1 r/w 0 yes 2 pwm3 (o) gpioa2 2 r/w 0 yes 3 pwm4 (o) gpioa3 3 r/w 0 yes 4 pwm5 (o) gpioa4 4 r/w 0 yes 5 pwm6 (o) gpioa5 5 r/w 0 yes 6 t1pwm_t1cmp (0) gpioa6 6 r/w 0 yes 7 t2pwm_t2cmp (0) gpioa7 7 r/w 0 yes 8 cap1_qep1 (i) gpioa8 8 r/w 0 yes 9 cap2_qep2 (i) gpioa9 9 r/w 0 yes 10 cap3_qepi1 (i) gpioa10 10 r/w 0 yes 11 tdira (i) gpioa11 11 r/w 0 yes 12 tclkina (i) gpioa12 12 r/w 0 yes 13 c1trip (i) gpioa13 13 r/w 0 yes 14 c2trip (i) gpioa14 14 r/w 0 yes 15 c3trip (i) gpioa15 15 r/w 0 yes pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 89 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 63. gpaqual register bit definitions bit name type reset description 7:0 qualprd r/w 0:0 specifies the qualification sampling period: 0x00 no qualification (just sync to sysclkout) 0x01 qualprd = sysclkout/2 0x02 qualprd = sysclkout/4 . 0xff qualprd = sysclkout/510 15:8 reserved r=0 0:0 notes: 1. gpadir bit = 0, configures corresponding gpio pin as an input. gpadir bit = 1, configures corresponding gpio pin as an output. 2. the gpadat, gpaset, gpaclear, gpatoggle registers have the same bit to i/o signal mapping as the gpamux and gpadir registers. 3. the gpadat register is a r/w register. reading the register will reflect the current state of the input i/o signal (after qualification). writing to the register will set the corresponding state of any i/o signal configured as an output. 4. the gpaset register is a write only register (reads back 0). writing a 1 to the corresponding bit of an i/o signal will cause the i/o signal to go high. writing a 0 will have no effect. 5. the gpaclear register is a write only register (reads back 0). writing a 1 to the corresponding bit of an i/o signal will cause the i/o signal to go low. writing a 0 will have no effect. 6. the gpatoggle register is a write only register (reads back 0). writing a 1 to the corresponding bit of an i/o signal will cause the i/o signal to toggle. writing a 0 will have no effect. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 90 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 64. gpbmux, gpbdir register bit definitions gpbmux bit peripheral name (bit = 1) gpio name (bit = 0) gpbdir bit type reset input qual ev-b peripheral 0 pwm7 (o) gpiob0 0 r/w 0 yes 1 pwm8 (o) gpiob1 1 r/w 0 yes 2 pwm9 (o) gpiob2 2 r/w 0 yes 3 pwm10 (o) gpiob3 3 r/w 0 yes 4 pwm11 (o) gpiob4 4 r/w 0 yes 5 pwm12 (o) gpiob5 5 r/w 0 yes 6 t3pwm_t3cmp (0) gpiob6 6 r/w 0 yes 7 t4pwm_t4cmp (0) gpiob7 7 r/w 0 yes 8 cap4_qep3 (i) gpiob8 8 r/w 0 yes 9 cap5_qep4 (i) gpiob9 9 r/w 0 yes 10 cap6_qepi2 (i) gpiob10 10 r/w 0 yes 11 tdirb (i) gpiob11 11 r/w 0 yes 12 tclkinb (i) gpiob12 12 r/w 0 yes 13 c4trip (i) gpiob13 13 r/w 0 yes 14 c5trip (i) gpiob14 14 r/w 0 yes 15 c6trip (i) gpiob15 15 r/w 0 yes table 65. gpbqual register bit definitions bit name type reset description 7:0 qualprd r/w 0:0 specifies the qualification sampling period: 0x00 no qualification (just sync to sysclkout) 0x01 qualprd = sysclkout/2 0x02 qualprd = sysclkout/4 . 0xff qualprd = sysclkout/510 15:8 reserved r=0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 91 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 66. gpdmux, gpddir register bit definitions gpdmux bit peripheral name (bit = 1) gpio name (bit = 0) gpddir bit type reset input qual ev-a peripheral: 0 t1ctrip_pdpinta (i) gpiod0 0 r/w 0 yes 1 t2ctrip (i) gpiod1 1 r/w 0 yes 2 reserved gpiod2 2 r/w 0 ? 3 reserved gpiod3 3 r/w 0 ? 4 reserved gpiod4 4 r/w 0 ? ev-b peripheral: 5 t3ctrip_pdpintb (i) gpiod5 5 r/w 0 yes 6 t4ctrip (i) gpiod6 6 r/w 0 yes 7 reserved gpiod7 7 r=0 0 ? 8 reserved gpiod8 8 r=0 0 ? 9 reserved gpiod9 9 r=0 0 ? 10 reserved gpiod10 10 r/w 0 ? 11 reserved gpiod11 11 r/w 0 ? 12 reserved gpiod12 12 r=0 0 ? 13 reserved gpiod13 13 r=0 0 ? 14 reserved gpiod14 14 r=0 0 ? 15 reserved gpiod15 15 r=0 0 ? table 67. gpdqual register bit definitions bit name type reset description 7:0 qualprd r/w 0:0 specifies the qualification sampling period: 0x00 no qualification (just sync to sysclkout) 0x01 qualprd = sysclkout/2 0x02 qualprd = sysclkout/4 . 0xff qualprd = sysclkout/510 15:8 reserved r=0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 92 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 68. gpemux, gpedir register bit definitions gpemux bit peripheral name (bit = 1) gpio name (bit = 0) gpedir bit type reset input qual interrupts: 0 xint1_xbio (i) gpioe0 0 r/w 0 yes 1 xint2_adcsoc (i) gpioe1 1 r/w 0 yes 2 xnmi_xint13 (i) gpioe2 2 r/w 0 yes 3 reserved gpioe3 3 r/w 0 ? 4 reserved gpioe4 4 r/w 0 ? 5 reserved gpioe5 5 r=0 0 ? 6 reserved gpioe6 6 r=0 0 ? 7 reserved gpioe7 7 r=0 0 ? 8 reserved gpioe8 8 r=0 0 ? 9 reserved gpioe9 9 r=0 0 ? 10 reserved gpioe10 10 r=0 0 ? 11 reserved gpioe11 11 r=0 0 ? 12 reserved gpioe12 12 r=0 0 ? 13 reserved gpioe13 13 r=0 0 ? 14 reserved gpioe14 14 r=0 0 ? 15 reserved gpioe15 15 r=0 0 ? table 69. gpequal register bit definitions bit name type reset description 7:0 qualprd r/w 0:0 specifies the qualification sampling period: 0x00 no qualification (just sync to sysclkout) 0x01 qualprd = sysclkout/2 0x02 qualprd = sysclkout/4 . 0xff qualprd = sysclkout/510 15:8 reserved r=0 0:0 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 93 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 70. gpfmux, gpfdir register bit defintions gpfmux bit peripheral name (bit = 1) gpio name (bit = 0) gpfdir bit type reset input qual spi peripheral: 0 spisimo (o) gpiof0 0 r/w 0 no 1 spisomi (i) gpiof1 1 r/w 0 no 2 spiclk (i/o) gpiof2 2 r/w 0 no 3 spiste (i/o) gpiof3 3 r/w 0 no scia peripheral: 4 scitxda (o) gpiof4 4 r/w 0 no 5 scirxda (i) gpiof5 5 r/w 0 no can peripheral: 6 cantx (o) gpiof6 6 r/w 0 no 7 canrx (i) gpiof7 7 r/w 0 no mcbsp peripheral: 8 mclkx (i/o) gpiof8 8 r/w 0 no 9 mclkr (i/o) gpiof9 9 r/w 0 no 10 mfsx (i/o) gpiof10 10 r/w 0 no 11 mfsr (i/o) gpiof11 11 r/w 0 no 12 mdx (o) gpiof12 12 r/w 0 no 13 mdr (i) gpiof13 13 r/w 0 no xint i/o space strobe & xf cpu output signal: 14 xf (0) gpiof14 14 r/w 0 no pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 94 post office box 1443 ? houston, texas 77251 ? 1443 gpio mux (continued) table 71. gpgmux, gpgdir register bit definitions gpgmux bit peripheral name (bit = 1) gpio name (bit = 0) gpgdir bit type reset input qual 0 reserved gpiog0 0 r/w 0 ? 1 reserved gpiog1 1 r/w 0 ? 2 reserved gpiog2 2 r/w 0 ? 3 reserved gpiog3 3 r/w 0 ? sci-b peripheral: 4 scitxdb (o) gpiog4 4 r/w 0 no 5 scirxdb (i) gpiog5 5 r/w 0 no 6 reserved gpiog6 6 r/w 0 ? 7 reserved gpiog7 7 r/w 0 ? 8 reserved gpiog8 8 r/w 0 ? 9 reserved gpiog9 9 r/w 0 ? 10 reserved gpiog10 10 r/w 0 ? 11 reserved gpiog11 11 r/w 0 ? 12 reserved gpiog12 12 r/w 0 ? 13 reserved gpiog13 13 r/w 0 ? 14 reserved gpiog14 14 r/w 0 ? 15 reserved gpiog15 15 r/w 0 ? pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 95 post office box 1443 ? houston, texas 77251 ? 1443 development support texas instruments (ti) offers an extensive line of development tools for the c28x ? generation of dsps, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of f2810- and f2812-based applications: software development tools: assembler/linker simulator optimizing ansi c compiler application algorithms c/c++/assembly debugger and code profiler hardware development tools: emulator xds510 ? /xds510pp ? (supports x24x/28x multiprocessor system debug) spi515 (third-party tool) xds510pp (third-party tool) the tms320 dsp development support reference guide (literature number spru011) contains information about development support products for all tms320 ? dsp family member devices, including documentation. refer to this document for further information about tms320 ? dsp documentation or any other tms320 ? dsp support products from texas instruments. there is also an additional document, the tms320 third-party support reference guide (literature number spru052), which contains information from other companies in the industry regarding products related to the tms320 ? dsps . to receive copies of tms320 ? dsp literature, contact the literature response center at 800-477-8924. development tools for the 28x are as follows: code composer studio ? integrated development environment (ide) version 2.0 ? code composer studio version 2.0 debugger ? code generation tools ? assembler/linker ? c/c++ compiler ? cycle accurate simulator jtag-based emulator sample applications code universal 5-v dc power supply documentation and cables pr o du c t preview xds510, xds510pp, tms320, and code composer studio are trademarks of texas instruments.
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 96 post office box 1443 ? houston, texas 77251 ? 1443 device and development support tool nomenclature to designate the stages in the product development cycle, texas instruments assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each tms320 ? dsp member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). this development flow is defined below. support tool development evolutionary flow: tmdx development support product that has not completed ti ? s internal qualification testing tmds fully qualified development support product tmx and tmp devices and tmdx development support tools are shipped against the following disclaimer: ? developmental product is intended for internal evaluation purposes. ? tms devices and tmds development support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. ti ? s standard warranty applies. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pbk) and temperature range (for example, a). figure 23 provides a legend for reading the complete device name for any tms320x28x family member. refer to the timing section for specific options that are available on f2810 and f2812 devices. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. prefix tms 320 f 2810 pbk tmx = experimental device tmp = prototype device tms = qualified device device family 320 = tms320 ? dsp family technology package type ? ghh = 179-pin microstar bga ? pgf = 176-pin lqfp pbk = 128-pin lqfp f = flash eeprom (1.8-v core/3.3-v i/o) device 2810 2812 ? bga = ball grid array lqfp = low-profile quad flatpack temperature range a= ? 40 c to 85 c s= ? 40 c to 125 c a figure 23. tms320x28x device nomenclature pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 97 post office box 1443 ? houston, texas 77251 ? 1443 documentation support extensive documentation supports all of the tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; and hardware and software applications. useful reference documentation includes: application reports ? 3.3v dsp for digital motor control (literature number spra550) a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 ? dsp newsletter, details on signal processing , is published quarterly and distributed to update tms320 ? dsp customers on product information. updated information on the tms320 ? dsp controllers can be found on the worldwide web at: http://www.ti.com . to send comments regarding this tms320f2810/tms320f2812 data sheet (literature number sprs174), use the comments@books.sc.ti.com email address, which is a repository for feedback. for questions and support, contact the product information center listed at the http://www.ti.com/sc/docs/pic/home.htm site. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 98 post office box 1443 ? houston, texas 77251 ? 1443 absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted) ? supply voltage range, v dd , pllv cca , v ddo , and v cca (see note 1) ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . supply voltage range, cv dd ? 0.5 v to 2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ccp range ? 0.3 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v in ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range,v o ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v in < 0 or v in > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature ranges, t a : a version ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s version ? 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . junction temperature range, t j ? 40 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? clamp current stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions ? min nom max unit v dd /v ddo supply voltage v ddo = v dd 0.3 v 3 3.3 3.6 v cv dd device supply voltage, cpu/core 1.65 1.8 1.95 v v ss supply ground 0 0 0 v pllv cca pll supply voltage 3 3.3 3.6 v v cca ? adc supply voltage 3 3.3 3.6 v v ccp flash programming supply voltage 3 3.3 3.6 v f clkout device clock frequency (system clock) 2 150 mhz v high level input voltage all inputs 2 v v ih high-level input voltage all inputs 2 v v low level input voltage all inputs 08 v v il low-level input voltage all inputs 0.8 v i oh high-level output source current, v oh = 2.4 v ? 2 ma i ol low-level output sink current, v ol = v ol max 2 ma t free air temperature a version ? 40 85 c t a free-air temperature s version ? 40 125 c t j junction temperature ? 40 25 150 c n f flash endurance for the array (write/erase cycles) ? 40 c to 85 c tbd cycles n otp otp endurance for the array (write cycles) ? 40 c to 85 c 1 cycles ? refer to the mechanical data package page for thermal resistance values, ja (junction-to-ambient) and jc (junction-to-case). the drive strength of the eva pwm pins and the evb pwm pins are not identical. ? v cca should not exceed v dd by 0.3 v. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 99 post office box 1443 ? houston, texas 77251 ? 1443 electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted) parameter test conditions min typ max unit v oh high level out p ut voltage v dd = 3.0 v, i oh = i oh max 2.4 v v oh high-level output voltage all outputs at 50 a v ddo ? 0.2 v v ol low-level output voltage i ol = i ol max 0.4 v i input current (low level) with pullup v33vv0v ? 16 a i il input current (low level) with pulldown v dd = 3.3 v, v in = 0 v 2 a i input current (high level) with pullup v33vvv 2 a i ih input current (high level) with pulldown v dd = 3.3 v, v in = v dd 16 a i oz output current, high-impedance state (off-state) v o = v dd or 0 v 2 a c i input capacitance 2 pf c o output capacitance 3 pf pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 100 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data ghh (s-pbga-n179) plastic ball grid array 10,40 typ 0,40 14 12 13 10 11 8 9 p m l j h k n 56 34 g e f d c 12 a b 7 seating plane 4173504-3/b 02/00 sq 12,10 11,90 0,95 0,35 0,45 0,45 0,55 0,85 0,12 0,08 1,40 max 0,80 0,80 0,40 0,10 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar bga ? configuration microstar bga is a trademark of texas instruments. pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 101 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data pgf (s-pqfp-g176) plastic quad flatpack 0,13 nom 89 0,17 0,27 88 45 0,45 0,25 0,75 44 seating plane 0,05 min 4040134 / b 11/96 gage plane 132 133 176 sq 24,20 sq 25,80 26,20 23,80 21,50 sq 1 1,45 1,35 1,60 max m 0,08 0,50 0,08 0 ? 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 pr o du c t preview
tms320f2810, tms320f2812 digital signal processors sprs174b ? april 2001 ? revised september 2001 102 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data pbk (s-pqfp-g128) plastic quad flatpack 4040279-3 / c 11/96 64 33 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,23 65 32 96 1 12,40 typ 0,13 97 128 sq sq 13,80 16,20 15,80 1,60 max 1,45 1,35 14,20 0 ? 7 0,08 0,40 m 0,07 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 pr o du c t preview
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer ? s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such products or services might be or are used. ti ? s publication of information regarding any third party ? s products or services does not constitute ti ? s approval, license, warranty or endorsement thereof. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. resale of ti ? s products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. also see: standard terms and conditions of sale for semiconductor products. www.ti.com/sc/docs/stdterms.htm mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated

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